Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

   1 * ARM SMMUv3 Architecture Implementation
   2
   3 The SMMUv3 architecture is a significant departure from previous
   4 revisions, replacing the MMIO register interface with in-memory command
   5 and event queues and adding support for the ATS and PRI components of
   6 the PCIe specification.
   7
   8 ** SMMUv3 required properties:
   9
  10 - compatible        : Should include:
  11
  12                       * "arm,smmu-v3" for any SMMUv3 compliant
  13                         implementation. This entry should be last in the
  14                         compatible list.
  15
  16 - reg               : Base address and size of the SMMU.
  17
  18 - interrupts        : Non-secure interrupt list describing the wired
  19                       interrupt sources corresponding to entries in
  20                       interrupt-names. If no wired interrupts are
  21                       present then this property may be omitted.
  22
  23 - interrupt-names   : When the interrupts property is present, should
  24                       include the following:
  25                       * "eventq"    - Event Queue not empty
  26                       * "priq"      - PRI Queue not empty
  27                       * "cmdq-sync" - CMD_SYNC complete
  28                       * "gerror"    - Global Error activated
  29                       * "combined"  - The combined interrupt is optional,
  30                                       and should only be provided if the
  31                                       hardware supports just a single,
  32                                       combined interrupt line.
  33                                       If provided, then the combined interrupt
  34                                       will be used in preference to any others.
  35
  36 - #iommu-cells      : See the generic IOMMU binding described in
  37                         devicetree/bindings/pci/pci-iommu.txt
  38                       for details. For SMMUv3, must be 1, with each cell
  39                       describing a single stream ID. All possible stream
  40                       IDs which a device may emit must be described.
  41
  42 ** SMMUv3 optional properties:
  43
  44 - dma-coherent      : Present if DMA operations made by the SMMU (page
  45                       table walks, stream table accesses etc) are cache
  46                       coherent with the CPU.
  47
  48                       NOTE: this only applies to the SMMU itself, not
  49                       masters connected upstream of the SMMU.
  50
  51 - msi-parent        : See the generic MSI binding described in
  52                         devicetree/bindings/interrupt-controller/msi.txt
  53                       for a description of the msi-parent property.
  54
  55 - hisilicon,broken-prefetch-cmd
  56                     : Avoid sending CMD_PREFETCH_* commands to the SMMU.
  57
  58 - cavium,cn9900-broken-page1-regspace
  59                     : Replaces all page 1 offsets used for EVTQ_PROD/CONS,
  60                       PRIQ_PROD/CONS register access with page 0 offsets.
  61                       Set for Cavium ThunderX2 silicon that doesn't support
  62                       SMMU page1 register space.
  63
  64 ** Example
  65
  66         smmu@2b400000 {
  67                 compatible = "arm,smmu-v3";
  68                 reg = <0x0 0x2b400000 0x0 0x20000>;
  69                 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
  70                              <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
  71                              <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
  72                              <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
  73                 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
  74                 dma-coherent;
  75                 #iommu-cells = <1>;
  76                 msi-parent = <&its 0xff0000>;
  77         };