1 * ARM Generic Interrupt Controller, version 3
3 AArch64 SMP cores are often associated with a GICv3, providing Private
4 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
5 Software Generated Interrupts (SGI), and Locality-specific Peripheral
8 Main node required properties:
10 - compatible : should at least contain "arm,gic-v3" or either
11 "qcom,msm8996-gic-v3", "arm,gic-v3" for msm8996 SoCs
12 to address SoC specific bugs/quirks
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
15 interrupt source. Must be a single cell with a value of at least 3.
16 If the system requires describing PPI affinity, then the value must
19 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
20 interrupts. Other values are reserved for future use.
22 The 2nd cell contains the interrupt number for the interrupt type.
23 SPI interrupts are in the range [0-987]. PPI interrupts are in the
26 The 3rd cell is the flags, encoded as follows:
27 bits[3:0] trigger type and level flags.
31 The 4th cell is a phandle to a node describing a set of CPUs this
32 interrupt is affine to. The interrupt must be a PPI, and the node
33 pointed must be a subnode of the "ppi-partitions" subnode. For
34 interrupt types other than PPI or PPIs that are not partitionned,
35 this cell must be zero. See the "ppi-partitions" node description
38 Cells 5 and beyond are reserved for future use and must have a value
41 - reg : Specifies base physical address(s) and size of the GIC
42 registers, in the following order:
43 - GIC Distributor interface (GICD)
44 - GIC Redistributors (GICR), one range per redistributor region
45 - GIC CPU interface (GICC)
46 - GIC Hypervisor interface (GICH)
47 - GIC Virtual CPU interface (GICV)
49 GICC, GICH and GICV are optional.
51 - interrupts : Interrupt source of the VGIC maintenance interrupt.
55 - redistributor-stride : If using padding pages, specifies the stride
56 of consecutive redistributors. Must be a multiple of 64kB.
58 - #redistributor-regions: The number of independent contiguous regions
59 occupied by the redistributors. Required if more than one such
62 - msi-controller: Boolean property. Identifies the node as an MSI
63 controller. Only present if the Message Based Interrupt
64 functionnality is being exposed by the HW, and the mbi-ranges
67 - mbi-ranges: A list of pairs <intid span>, where "intid" is the first
68 SPI of a range that can be used an MBI, and "span" the size of that
69 range. Multiple ranges can be provided. Requires "msi-controller" to
72 - mbi-alias: Address property. Base address of an alias of the GICD
73 region containing only the {SET,CLR}SPI registers to be used if
74 isolation is required, and if supported by the HW.
78 PPI affinity can be expressed as a single "ppi-partitions" node,
79 containing a set of sub-nodes, each with the following property:
80 - affinity: Should be a list of phandles to CPU nodes (as described in
81 Documentation/devicetree/bindings/arm/cpus.txt).
83 GICv3 has one or more Interrupt Translation Services (ITS) that are
84 used to route Message Signalled Interrupts (MSI) to the CPUs.
86 These nodes must have the following properties:
87 - compatible : Should at least contain "arm,gic-v3-its".
88 - msi-controller : Boolean property. Identifies the node as an MSI controller
89 - #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device
90 which will generate the MSI.
91 - reg: Specifies the base physical address and size of the ITS
95 - socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated
96 address and size of the pre-ITS window.
98 The main GIC node must contain the appropriate #address-cells,
99 #size-cells and ranges properties for the reg property of all ITS
104 gic: interrupt-controller@2cf00000 {
105 compatible = "arm,gic-v3";
106 #interrupt-cells = <3>;
107 #address-cells = <2>;
110 interrupt-controller;
111 reg = <0x0 0x2f000000 0 0x10000>, // GICD
112 <0x0 0x2f100000 0 0x200000>, // GICR
113 <0x0 0x2c000000 0 0x2000>, // GICC
114 <0x0 0x2c010000 0 0x2000>, // GICH
115 <0x0 0x2c020000 0 0x2000>; // GICV
116 interrupts = <1 9 4>;
119 mbi-ranges = <256 128>;
122 compatible = "arm,gic-v3-its";
125 reg = <0x0 0x2c200000 0 0x20000>;
129 gic: interrupt-controller@2c010000 {
130 compatible = "arm,gic-v3";
131 #interrupt-cells = <4>;
132 #address-cells = <2>;
135 interrupt-controller;
136 redistributor-stride = <0x0 0x40000>; // 256kB stride
137 #redistributor-regions = <2>;
138 reg = <0x0 0x2c010000 0 0x10000>, // GICD
139 <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
140 <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
141 <0x0 0x2c040000 0 0x2000>, // GICC
142 <0x0 0x2c060000 0 0x2000>, // GICH
143 <0x0 0x2c080000 0 0x2000>; // GICV
144 interrupts = <1 9 4>;
147 compatible = "arm,gic-v3-its";
150 reg = <0x0 0x2c200000 0 0x20000>;
154 compatible = "arm,gic-v3-its";
157 reg = <0x0 0x2c400000 0 0x20000>;
161 part0: interrupt-partition-0 {
162 affinity = <&cpu0 &cpu2>;
165 part1: interrupt-partition-1 {
166 affinity = <&cpu1 &cpu3>;
174 interrupts = <1 1 4 &part0>;