1 * Amlogic Meson SAR (Successive Approximation Register) A/D converter
4 - compatible: depending on the SoC this should be one of:
5 - "amlogic,meson8-saradc" for Meson8
6 - "amlogic,meson8b-saradc" for Meson8b
7 - "amlogic,meson8m2-saradc" for Meson8m2
8 - "amlogic,meson-gxbb-saradc" for GXBB
9 - "amlogic,meson-gxl-saradc" for GXL
10 - "amlogic,meson-gxm-saradc" for GXM
11 - "amlogic,meson-axg-saradc" for AXG
12 along with the generic "amlogic,meson-saradc"
13 - reg: the physical base address and length of the registers
14 - interrupts: the interrupt indicating end of sampling
15 - clocks: phandle and clock identifier (see clock-names)
16 - clock-names: mandatory clocks:
17 - "clkin" for the reference clock (typically XTAL)
18 - "core" for the SAR ADC core clock
20 - "adc_clk" for the ADC (sampling) clock
21 - "adc_sel" for the ADC (sampling) clock mux
22 - vref-supply: the regulator supply for the ADC reference voltage
23 - #io-channel-cells: must be 1, see ../iio-bindings.txt
26 - nvmem-cells: phandle to the temperature_calib eFuse cells
27 - nvmem-cell-names: if present (to enable the temperature sensor
28 calibration) this must contain "temperature_calib"
33 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
34 #io-channel-cells = <1>;
35 reg = <0x0 0x8680 0x0 0x34>;
36 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
38 <&clkc CLKID_SAR_ADC>,
40 <&clkc CLKID_SAR_ADC_CLK>,
41 <&clkc CLKID_SAR_ADC_SEL>;
42 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";