Documentation/devicetree/bindings/i2c/i2c-at91.txt

   1 I2C for Atmel platforms
   2
   3 Required properties :
   4 - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
   5      "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
   6      "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c", "atmel,sama5d2-i2c" or
   7      "microchip,sam9x60-i2c"
   8 - reg: physical base address of the controller and length of memory mapped
   9      region.
  10 - interrupts: interrupt number to the cpu.
  11 - #address-cells = <1>;
  12 - #size-cells = <0>;
  13 - clocks: phandles to input clocks.
  14
  15 Optional properties:
  16 - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
  17 - dmas: A list of two dma specifiers, one for each entry in dma-names.
  18 - dma-names: should contain "tx" and "rx".
  19 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
  20   capable I2C controllers.
  21 - i2c-sda-hold-time-ns: TWD hold time, only available for:
  22         "atmel,sama5d4-i2c",
  23         "atmel,sama5d2-i2c",
  24         "microchip,sam9x60-i2c".
  25 - Child nodes conforming to i2c bus binding
  26
  27 Examples :
  28
  29 i2c0: i2c@fff84000 {
  30         compatible = "atmel,at91sam9g20-i2c";
  31         reg = <0xfff84000 0x100>;
  32         interrupts = <12 4 6>;
  33         #address-cells = <1>;
  34         #size-cells = <0>;
  35         clocks = <&twi0_clk>;
  36         clock-frequency = <400000>;
  37
  38         24c512@50 {
  39                 compatible = "atmel,24c512";
  40                 reg = <0x50>;
  41                 pagesize = <128>;
  42         }
  43 }
  44
  45 i2c0: i2c@f8034600 {
  46         compatible = "atmel,sama5d2-i2c";
  47         reg = <0xf8034600 0x100>;
  48         interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
  49         dmas = <&dma0
  50                 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
  51                 AT91_XDMAC_DT_PERID(11)>,
  52                <&dma0
  53                 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
  54                 AT91_XDMAC_DT_PERID(12)>;
  55         dma-names = "tx", "rx";
  56         #address-cells = <1>;
  57         #size-cells = <0>;
  58         clocks = <&flx0>;
  59         atmel,fifo-size = <16>;
  60         i2c-sda-hold-time-ns = <336>;
  61
  62         wm8731: wm8731@1a {
  63                 compatible = "wm8731";
  64                 reg = <0x1a>;
  65         };
  66 };