1 NVIDIA Tegra Graphics Processing Units
4 - compatible: "nvidia,<gpu>"
5 Currently recognized values:
9 - reg: Physical base address and length of the controller's registers.
10 Must contain two entries:
11 - first entry for bar0
12 - second entry for bar1
13 - interrupts: Must contain an entry for each entry in interrupt-names.
14 See ../interrupt-controller/interrupts.txt for details.
15 - interrupt-names: Must include the following entries:
18 - vdd-supply: regulator for supply voltage. Only required for GPUs not using
20 - clocks: Must contain an entry for each entry in clock-names.
21 See ../clocks/clock-bindings.txt for details.
22 - clock-names: Must include the following entries:
25 If the compatible string is "nvidia,gm20b", then the following clock
28 - resets: Must contain an entry for each entry in reset-names.
29 See ../reset/reset.txt for details.
30 - reset-names: Must include the following entries:
32 - power-domains: GPUs that make use of power domains can define this property
33 instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
36 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
41 compatible = "nvidia,gk20a";
42 reg = <0x0 0x57000000 0x0 0x01000000>,
43 <0x0 0x58000000 0x0 0x01000000>;
44 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
46 interrupt-names = "stall", "nonstall";
47 vdd-supply = <&vdd_gpu>;
48 clocks = <&tegra_car TEGRA124_CLK_GPU>,
49 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
50 clock-names = "gpu", "pwr";
51 resets = <&tegra_car 184>;
53 iommus = <&mc TEGRA_SWGROUP_GPU>;
60 compatible = "nvidia,gm20b";
61 reg = <0x0 0x57000000 0x0 0x01000000>,
62 <0x0 0x58000000 0x0 0x01000000>;
63 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
65 interrupt-names = "stall", "nonstall";
66 clocks = <&tegra_car TEGRA210_CLK_GPU>,
67 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
68 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
69 clock-names = "gpu", "pwr", "ref";
70 resets = <&tegra_car 184>;
72 iommus = <&mc TEGRA_SWGROUP_GPU>;
79 compatible = "nvidia,gp10b";
80 reg = <0x0 0x17000000 0x0 0x1000000>,
81 <0x0 0x18000000 0x0 0x1000000>;
82 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
83 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-names = "stall", "nonstall";
85 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
86 <&bpmp TEGRA186_CLK_GPU>;
87 clock-names = "gpu", "pwr";
88 resets = <&bpmp TEGRA186_RESET_GPU>;
90 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
91 iommus = <&smmu TEGRA186_SID_GPU>;