Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt

   1 ARM Mali Utgard GPU
   2 ===================
   3
   4 Required properties:
   5   - compatible
   6     * Must be one of the following:
   7       + "arm,mali-300"
   8       + "arm,mali-400"
   9       + "arm,mali-450"
  10     * And, optionally, one of the vendor specific compatible:
  11       + allwinner,sun4i-a10-mali
  12       + allwinner,sun7i-a20-mali
  13       + allwinner,sun50i-h5-mali
  14       + amlogic,meson-gxbb-mali
  15       + amlogic,meson-gxl-mali
  16       + rockchip,rk3036-mali
  17       + rockchip,rk3066-mali
  18       + rockchip,rk3188-mali
  19       + rockchip,rk3228-mali
  20       + stericsson,db8500-mali
  21
  22   - reg: Physical base address and length of the GPU registers
  23
  24   - interrupts: an entry for each entry in interrupt-names.
  25     See ../interrupt-controller/interrupts.txt for details.
  26
  27   - interrupt-names:
  28     * ppX: Pixel Processor X interrupt (X from 0 to 7)
  29     * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
  30     * pp: Pixel Processor broadcast interrupt (mali-450 only)
  31     * gp: Geometry Processor interrupt
  32     * gpmmu: Geometry Processor MMU interrupt
  33
  34   - clocks: an entry for each entry in clock-names
  35   - clock-names:
  36     * bus: bus clock for the GPU
  37     * core: clock driving the GPU itself
  38
  39 Optional properties:
  40   - interrupt-names and interrupts:
  41     * pmu: Power Management Unit interrupt, if implemented in hardware
  42
  43   - memory-region:
  44     Memory region to allocate from, as defined in
  45     Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
  46
  47   - mali-supply:
  48     Phandle to regulator for the Mali device, as defined in
  49     Documentation/devicetree/bindings/regulator/regulator.txt for details.
  50
  51   - operating-points-v2:
  52     Operating Points for the GPU, as defined in
  53     Documentation/devicetree/bindings/opp/opp.txt
  54
  55   - power-domains:
  56     A power domain consumer specifier as defined in
  57     Documentation/devicetree/bindings/power/power_domain.txt
  58
  59 Vendor-specific bindings
  60 ------------------------
  61
  62 The Mali GPU is integrated very differently from one SoC to
  63 another. In order to accomodate those differences, you have the option
  64 to specify one more vendor-specific compatible, among:
  65
  66   - allwinner,sun4i-a10-mali
  67     Required properties:
  68       * resets: phandle to the reset line for the GPU
  69
  70   - allwinner,sun7i-a20-mali
  71     Required properties:
  72       * resets: phandle to the reset line for the GPU
  73
  74   - allwinner,sun50i-h5-mali
  75     Required properties:
  76       * resets: phandle to the reset line for the GPU
  77
  78   - Rockchip variants:
  79     Required properties:
  80       * resets: phandle to the reset line for the GPU
  81
  82   - stericsson,db8500-mali
  83     Required properties:
  84       * interrupt-names and interrupts:
  85         + combined: combined interrupt of all of the above lines
  86
  87 Example:
  88
  89 mali: gpu@1c40000 {
  90         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
  91         reg = <0x01c40000 0x10000>;
  92         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
  93                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
  94                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
  95                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  96                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  97                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
  98                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  99         interrupt-names = "gp",
 100                           "gpmmu",
 101                           "pp0",
 102                           "ppmmu0",
 103                           "pp1",
 104                           "ppmmu1",
 105                           "pmu";
 106         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 107         clock-names = "bus", "core";
 108         resets = <&ccu RST_BUS_GPU>;
 109 };
 110