Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt

   1 ARM Mali Utgard GPU
   2 ===================
   3
   4 Required properties:
   5   - compatible
   6     * Must be one of the following:
   7       + "arm,mali-300"
   8       + "arm,mali-400"
   9       + "arm,mali-450"
  10     * And, optionally, one of the vendor specific compatible:
  11       + allwinner,sun4i-a10-mali
  12       + allwinner,sun7i-a20-mali
  13       + allwinner,sun8i-h3-mali
  14       + allwinner,sun50i-a64-mali
  15       + allwinner,sun50i-h5-mali
  16       + amlogic,meson8-mali
  17       + amlogic,meson8b-mali
  18       + amlogic,meson-gxbb-mali
  19       + amlogic,meson-gxl-mali
  20       + rockchip,rk3036-mali
  21       + rockchip,rk3066-mali
  22       + rockchip,rk3188-mali
  23       + rockchip,rk3228-mali
  24       + rockchip,rk3328-mali
  25       + stericsson,db8500-mali
  26
  27   - reg: Physical base address and length of the GPU registers
  28
  29   - interrupts: an entry for each entry in interrupt-names.
  30     See ../interrupt-controller/interrupts.txt for details.
  31
  32   - interrupt-names:
  33     * ppX: Pixel Processor X interrupt (X from 0 to 7)
  34     * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
  35     * pp: Pixel Processor broadcast interrupt (mali-450 only)
  36     * gp: Geometry Processor interrupt
  37     * gpmmu: Geometry Processor MMU interrupt
  38
  39   - clocks: an entry for each entry in clock-names
  40   - clock-names:
  41     * bus: bus clock for the GPU
  42     * core: clock driving the GPU itself
  43
  44 Optional properties:
  45   - interrupt-names and interrupts:
  46     * pmu: Power Management Unit interrupt, if implemented in hardware
  47
  48   - memory-region:
  49     Memory region to allocate from, as defined in
  50     Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
  51
  52   - mali-supply:
  53     Phandle to regulator for the Mali device, as defined in
  54     Documentation/devicetree/bindings/regulator/regulator.txt for details.
  55
  56   - operating-points-v2:
  57     Operating Points for the GPU, as defined in
  58     Documentation/devicetree/bindings/opp/opp.txt
  59
  60   - power-domains:
  61     A power domain consumer specifier as defined in
  62     Documentation/devicetree/bindings/power/power_domain.txt
  63
  64 Vendor-specific bindings
  65 ------------------------
  66
  67 The Mali GPU is integrated very differently from one SoC to
  68 another. In order to accomodate those differences, you have the option
  69 to specify one more vendor-specific compatible, among:
  70
  71   - allwinner,sun4i-a10-mali
  72     Required properties:
  73       * resets: phandle to the reset line for the GPU
  74
  75   - allwinner,sun7i-a20-mali
  76     Required properties:
  77       * resets: phandle to the reset line for the GPU
  78
  79   - allwinner,sun50i-a64-mali
  80     Required properties:
  81       * resets: phandle to the reset line for the GPU
  82
  83   - allwinner,sun50i-h5-mali
  84     Required properties:
  85       * resets: phandle to the reset line for the GPU
  86
  87   - amlogic,meson8-mali and amlogic,meson8b-mali
  88     Required properties:
  89       * resets: phandle to the reset line for the GPU
  90
  91   - Rockchip variants:
  92     Required properties:
  93       * resets: phandle to the reset line for the GPU
  94
  95   - stericsson,db8500-mali
  96     Required properties:
  97       * interrupt-names and interrupts:
  98         + combined: combined interrupt of all of the above lines
  99
 100 Example:
 101
 102 mali: gpu@1c40000 {
 103         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
 104         reg = <0x01c40000 0x10000>;
 105         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 106                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 107                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 108                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 109                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 110                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 111                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 112         interrupt-names = "gp",
 113                           "gpmmu",
 114                           "pp0",
 115                           "ppmmu0",
 116                           "pp1",
 117                           "ppmmu1",
 118                           "pmu";
 119         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 120         clock-names = "bus", "core";
 121         resets = <&ccu RST_BUS_GPU>;
 122 };
 123