Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt

   1 ARM Mali Utgard GPU
   2 ===================
   3
   4 Required properties:
   5   - compatible
   6     * Must be one of the following:
   7       + "arm,mali-300"
   8       + "arm,mali-400"
   9       + "arm,mali-450"
  10     * And, optionally, one of the vendor specific compatible:
  11       + allwinner,sun4i-a10-mali
  12       + allwinner,sun7i-a20-mali
  13       + allwinner,sun8i-h3-mali
  14       + allwinner,sun50i-a64-mali
  15       + allwinner,sun50i-h5-mali
  16       + amlogic,meson-gxbb-mali
  17       + amlogic,meson-gxl-mali
  18       + rockchip,rk3036-mali
  19       + rockchip,rk3066-mali
  20       + rockchip,rk3188-mali
  21       + rockchip,rk3228-mali
  22       + rockchip,rk3328-mali
  23       + stericsson,db8500-mali
  24
  25   - reg: Physical base address and length of the GPU registers
  26
  27   - interrupts: an entry for each entry in interrupt-names.
  28     See ../interrupt-controller/interrupts.txt for details.
  29
  30   - interrupt-names:
  31     * ppX: Pixel Processor X interrupt (X from 0 to 7)
  32     * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
  33     * pp: Pixel Processor broadcast interrupt (mali-450 only)
  34     * gp: Geometry Processor interrupt
  35     * gpmmu: Geometry Processor MMU interrupt
  36
  37   - clocks: an entry for each entry in clock-names
  38   - clock-names:
  39     * bus: bus clock for the GPU
  40     * core: clock driving the GPU itself
  41
  42 Optional properties:
  43   - interrupt-names and interrupts:
  44     * pmu: Power Management Unit interrupt, if implemented in hardware
  45
  46   - memory-region:
  47     Memory region to allocate from, as defined in
  48     Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
  49
  50   - mali-supply:
  51     Phandle to regulator for the Mali device, as defined in
  52     Documentation/devicetree/bindings/regulator/regulator.txt for details.
  53
  54   - operating-points-v2:
  55     Operating Points for the GPU, as defined in
  56     Documentation/devicetree/bindings/opp/opp.txt
  57
  58   - power-domains:
  59     A power domain consumer specifier as defined in
  60     Documentation/devicetree/bindings/power/power_domain.txt
  61
  62 Vendor-specific bindings
  63 ------------------------
  64
  65 The Mali GPU is integrated very differently from one SoC to
  66 another. In order to accomodate those differences, you have the option
  67 to specify one more vendor-specific compatible, among:
  68
  69   - allwinner,sun4i-a10-mali
  70     Required properties:
  71       * resets: phandle to the reset line for the GPU
  72
  73   - allwinner,sun7i-a20-mali
  74     Required properties:
  75       * resets: phandle to the reset line for the GPU
  76
  77   - allwinner,sun50i-a64-mali
  78     Required properties:
  79       * resets: phandle to the reset line for the GPU
  80
  81   - allwinner,sun50i-h5-mali
  82     Required properties:
  83       * resets: phandle to the reset line for the GPU
  84
  85   - Rockchip variants:
  86     Required properties:
  87       * resets: phandle to the reset line for the GPU
  88
  89   - stericsson,db8500-mali
  90     Required properties:
  91       * interrupt-names and interrupts:
  92         + combined: combined interrupt of all of the above lines
  93
  94 Example:
  95
  96 mali: gpu@1c40000 {
  97         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
  98         reg = <0x01c40000 0x10000>;
  99         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 100                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 101                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 102                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 103                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 104                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 105                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 106         interrupt-names = "gp",
 107                           "gpmmu",
 108                           "pp0",
 109                           "ppmmu0",
 110                           "pp1",
 111                           "ppmmu1",
 112                           "pmu";
 113         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 114         clock-names = "bus", "core";
 115         resets = <&ccu RST_BUS_GPU>;
 116 };
 117