Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt

   1 ARM Mali Midgard GPU
   2 ====================
   3
   4 Required properties:
   5
   6 - compatible :
   7   * Must contain one of the following:
   8     + "arm,mali-t604"
   9     + "arm,mali-t624"
  10     + "arm,mali-t628"
  11     + "arm,mali-t720"
  12     + "arm,mali-t760"
  13     + "arm,mali-t820"
  14     + "arm,mali-t830"
  15     + "arm,mali-t860"
  16     + "arm,mali-t880"
  17   * which must be preceded by one of the following vendor specifics:
  18     + "amlogic,meson-gxm-mali"
  19     + "rockchip,rk3288-mali"
  20     + "rockchip,rk3399-mali"
  21
  22 - reg : Physical base address of the device and length of the register area.
  23
  24 - interrupts : Contains the three IRQ lines required by Mali Midgard devices.
  25
  26 - interrupt-names : Contains the names of IRQ resources in the order they were
  27   provided in the interrupts property. Must contain: "job", "mmu", "gpu".
  28
  29
  30 Optional properties:
  31
  32 - clocks : Phandle to clock for the Mali Midgard device.
  33
  34 - clock-names : Specify the names of the clocks specified in clocks
  35   when multiple clocks are present.
  36     * core: clock driving the GPU itself (When only one clock is present,
  37       assume it's this clock.)
  38     * bus: bus clock for the GPU
  39
  40 - mali-supply : Phandle to regulator for the Mali device. Refer to
  41   Documentation/devicetree/bindings/regulator/regulator.txt for details.
  42
  43 - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
  44   for details.
  45
  46 - #cooling-cells: Refer to Documentation/devicetree/bindings/thermal/thermal.txt
  47   for details.
  48
  49 Example for a Mali-T760:
  50
  51 gpu@ffa30000 {
  52         compatible = "rockchip,rk3288-mali", "arm,mali-t760";
  53         reg = <0xffa30000 0x10000>;
  54         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  55                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  56                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  57         interrupt-names = "job", "mmu", "gpu";
  58         clocks = <&cru ACLK_GPU>;
  59         mali-supply = <&vdd_gpu>;
  60         operating-points-v2 = <&gpu_opp_table>;
  61         power-domains = <&power RK3288_PD_GPU>;
  62         #cooling-cells = <2>;
  63 };
  64
  65 gpu_opp_table: opp_table0 {
  66         compatible = "operating-points-v2";
  67
  68         opp@533000000 {
  69                 opp-hz = /bits/ 64 <533000000>;
  70                 opp-microvolt = <1250000>;
  71         };
  72         opp@450000000 {
  73                 opp-hz = /bits/ 64 <450000000>;
  74                 opp-microvolt = <1150000>;
  75         };
  76         opp@400000000 {
  77                 opp-hz = /bits/ 64 <400000000>;
  78                 opp-microvolt = <1125000>;
  79         };
  80         opp@350000000 {
  81                 opp-hz = /bits/ 64 <350000000>;
  82                 opp-microvolt = <1075000>;
  83         };
  84         opp@266000000 {
  85                 opp-hz = /bits/ 64 <266000000>;
  86                 opp-microvolt = <1025000>;
  87         };
  88         opp@160000000 {
  89                 opp-hz = /bits/ 64 <160000000>;
  90                 opp-microvolt = <925000>;
  91         };
  92         opp@100000000 {
  93                 opp-hz = /bits/ 64 <100000000>;
  94                 opp-microvolt = <912500>;
  95         };
  96 };