Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt

   1 ARM Mali Midgard GPU
   2 ====================
   3
   4 Required properties:
   5
   6 - compatible :
   7   * Must contain one of the following:
   8     + "arm,mali-t604"
   9     + "arm,mali-t624"
  10     + "arm,mali-t628"
  11     + "arm,mali-t720"
  12     + "arm,mali-t760"
  13     + "arm,mali-t820"
  14     + "arm,mali-t830"
  15     + "arm,mali-t860"
  16     + "arm,mali-t880"
  17   * which must be preceded by one of the following vendor specifics:
  18     + "amlogic,meson-gxm-mali"
  19     + "rockchip,rk3288-mali"
  20     + "rockchip,rk3399-mali"
  21
  22 - reg : Physical base address of the device and length of the register area.
  23
  24 - interrupts : Contains the three IRQ lines required by Mali Midgard devices.
  25
  26 - interrupt-names : Contains the names of IRQ resources in the order they were
  27   provided in the interrupts property. Must contain: "job", "mmu", "gpu".
  28
  29
  30 Optional properties:
  31
  32 - clocks : Phandle to clock for the Mali Midgard device.
  33
  34 - mali-supply : Phandle to regulator for the Mali device. Refer to
  35   Documentation/devicetree/bindings/regulator/regulator.txt for details.
  36
  37 - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
  38   for details.
  39
  40 - resets : Phandle of the GPU reset line.
  41
  42 Vendor-specific bindings
  43 ------------------------
  44
  45 The Mali GPU is integrated very differently from one SoC to
  46 another. In order to accomodate those differences, you have the option
  47 to specify one more vendor-specific compatible, among:
  48
  49 - "amlogic,meson-gxm-mali"
  50   Required properties:
  51   - resets : Should contain phandles of :
  52     + GPU reset line
  53     + GPU APB glue reset line
  54
  55 Example for a Mali-T760:
  56
  57 gpu@ffa30000 {
  58         compatible = "rockchip,rk3288-mali", "arm,mali-t760";
  59         reg = <0xffa30000 0x10000>;
  60         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  61                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  62                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  63         interrupt-names = "job", "mmu", "gpu";
  64         clocks = <&cru ACLK_GPU>;
  65         mali-supply = <&vdd_gpu>;
  66         operating-points-v2 = <&gpu_opp_table>;
  67         power-domains = <&power RK3288_PD_GPU>;
  68 };
  69
  70 gpu_opp_table: opp_table0 {
  71         compatible = "operating-points-v2";
  72
  73         opp@533000000 {
  74                 opp-hz = /bits/ 64 <533000000>;
  75                 opp-microvolt = <1250000>;
  76         };
  77         opp@450000000 {
  78                 opp-hz = /bits/ 64 <450000000>;
  79                 opp-microvolt = <1150000>;
  80         };
  81         opp@400000000 {
  82                 opp-hz = /bits/ 64 <400000000>;
  83                 opp-microvolt = <1125000>;
  84         };
  85         opp@350000000 {
  86                 opp-hz = /bits/ 64 <350000000>;
  87                 opp-microvolt = <1075000>;
  88         };
  89         opp@266000000 {
  90                 opp-hz = /bits/ 64 <266000000>;
  91                 opp-microvolt = <1025000>;
  92         };
  93         opp@160000000 {
  94                 opp-hz = /bits/ 64 <160000000>;
  95                 opp-microvolt = <925000>;
  96         };
  97         opp@100000000 {
  98                 opp-hz = /bits/ 64 <100000000>;
  99                 opp-microvolt = <912500>;
 100         };
 101 };