Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt

   1 ARM Mali Bifrost GPU
   2 ====================
   3
   4 Required properties:
   5
   6 - compatible :
   7   * Since Mali Bifrost GPU model/revision is fully discoverable by reading
   8     some determined registers, must contain the following:
   9     + "arm,mali-bifrost"
  10   * which must be preceded by one of the following vendor specifics:
  11     + "amlogic,meson-g12a-mali"
  12
  13 - reg : Physical base address of the device and length of the register area.
  14
  15 - interrupts : Contains the three IRQ lines required by Mali Bifrost devices,
  16   in the following defined order.
  17
  18 - interrupt-names : Contains the names of IRQ resources in this exact defined
  19   order: "job", "mmu", "gpu".
  20
  21 Optional properties:
  22
  23 - clocks : Phandle to clock for the Mali Bifrost device.
  24
  25 - mali-supply : Phandle to regulator for the Mali device. Refer to
  26   Documentation/devicetree/bindings/regulator/regulator.txt for details.
  27
  28 - operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
  29   for details.
  30
  31 - resets : Phandle of the GPU reset line.
  32
  33 Vendor-specific bindings
  34 ------------------------
  35
  36 The Mali GPU is integrated very differently from one SoC to
  37 another. In order to accommodate those differences, you have the option
  38 to specify one more vendor-specific compatible, among:
  39
  40 - "amlogic,meson-g12a-mali"
  41   Required properties:
  42   - resets : Should contain phandles of :
  43     + GPU reset line
  44     + GPU APB glue reset line
  45
  46 Example for a Mali-G31:
  47
  48 gpu@ffa30000 {
  49         compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
  50         reg = <0xffe40000 0x10000>;
  51         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  52                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  53                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
  54         interrupt-names = "job", "mmu", "gpu";
  55         clocks = <&clk CLKID_MALI>;
  56         mali-supply = <&vdd_gpu>;
  57         operating-points-v2 = <&gpu_opp_table>;
  58         resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
  59 };
  60
  61 gpu_opp_table: opp_table0 {
  62         compatible = "operating-points-v2";
  63
  64         opp@533000000 {
  65                 opp-hz = /bits/ 64 <533000000>;
  66                 opp-microvolt = <1250000>;
  67         };
  68         opp@450000000 {
  69                 opp-hz = /bits/ 64 <450000000>;
  70                 opp-microvolt = <1150000>;
  71         };
  72         opp@400000000 {
  73                 opp-hz = /bits/ 64 <400000000>;
  74                 opp-microvolt = <1125000>;
  75         };
  76         opp@350000000 {
  77                 opp-hz = /bits/ 64 <350000000>;
  78                 opp-microvolt = <1075000>;
  79         };
  80         opp@266000000 {
  81                 opp-hz = /bits/ 64 <266000000>;
  82                 opp-microvolt = <1025000>;
  83         };
  84         opp@160000000 {
  85                 opp-hz = /bits/ 64 <160000000>;
  86                 opp-microvolt = <925000>;
  87         };
  88         opp@100000000 {
  89                 opp-hz = /bits/ 64 <100000000>;
  90                 opp-microvolt = <912500>;
  91         };
  92 };