1 Specifying GPIO information for devices
2 =======================================
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
9 for compatibility reasons (resolving to the "gpios" property), it is not allowed
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
11 bindings use it, but are only supported for compatibility reasons and should not
12 be used for newer bindings since it has been deprecated.
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
15 cases should they contain more than one. If your device uses several GPIOs with
16 distinct functions, reference each of them under its own property, giving it a
17 meaningful name. The only case where an array of GPIOs is accepted is when
18 several GPIOs serve the same function (e.g. a parallel data line).
20 The exact purpose of each gpios property must be documented in the device tree
21 binding of the device.
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
32 data-gpios = <&gpio1 12 0>,
37 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
38 a local offset to the GPIO line and the second cell represent consumer flags,
39 such as if the consumer desire the line to be active low (inverted) or open
40 drain. This is the recommended practice.
42 The exact meaning of each specifier cell is controller specific, and must be
43 documented in the device tree binding for the device, but it is strongly
44 recommended to use the two-cell approach.
46 Most controllers are specifying a generic flag bitfield in the last cell, so
47 for these, use the macros defined in
48 include/dt-bindings/gpio/gpio.h whenever possible:
50 Example of a node using GPIOs:
53 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
56 GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
57 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
59 Optional standard bitfield specifiers for the last cell:
61 - Bit 0: 0 means active high, 1 means active low
62 - Bit 1: 0 mean push-pull wiring, see:
63 https://en.wikipedia.org/wiki/Push-pull_output
64 1 means single-ended wiring, see:
65 https://en.wikipedia.org/wiki/Single-ended_triode
66 - Bit 2: 0 means open-source, 1 means open drain, see:
67 https://en.wikipedia.org/wiki/Open_collector
68 - Bit 3: 0 means the output should be maintained during sleep/low-power mode
69 1 means the output state can be lost during sleep/low-power mode
71 1.1) GPIO specifier best practices
72 ----------------------------------
74 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
75 high or active-low. If it does, the following best practices should be
78 The gpio-specifier's polarity flag should represent the physical level at the
79 GPIO controller that achieves (or represents, for inputs) a logically asserted
80 value at the device. The exact definition of logically asserted should be
81 defined by the binding for the device. If the board inverts the signal between
82 the GPIO controller and the device, then the gpio-specifier will represent the
83 opposite physical level than the signal at the device's pin.
85 When the device's signal polarity is configurable, the binding for the
88 a) Define a single static polarity for the signal, with the expectation that
89 any software using that binding would statically program the device to use
92 The static choice of polarity may be either:
94 a1) (Preferred) Dictated by a binding-specific DT property.
98 a2) Defined statically by the DT binding itself.
100 In particular, the polarity cannot be derived from the gpio-specifier, since
101 that would prevent the DT from separately representing the two orthogonal
102 concepts of configurable signal polarity in the device, and possible board-
103 level signal inversion.
107 b) Pick a single option for device signal polarity, and document this choice
108 in the binding. The gpio-specifier should represent the polarity of the signal
109 (at the GPIO controller) assuming that the device is configured for this
110 particular signal polarity choice. If software chooses to program the device
111 to generate or receive a signal of the opposite polarity, software will be
112 responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
115 2) gpio-controller nodes
116 ------------------------
118 Every GPIO controller node must contain both an empty "gpio-controller"
119 property, and a #gpio-cells integer property, which indicates the number of
120 cells in a gpio-specifier.
122 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
123 instance of a hardware IP core on a silicon die, usually exposed to the
124 programmer as a coherent range of I/O addresses. Usually each such bank is
125 exposed in the device tree as an individual gpio-controller node, reflecting
126 the fact that the hardware was synthesized by reusing the same IP block a
129 Optionally, a GPIO controller may have a "ngpios" property. This property
130 indicates the number of in-use slots of available slots for GPIOs. The
131 typical example is something like this: the hardware register is 32 bits
132 wide, but only 18 of the bits have a physical counterpart. The driver is
133 generally written so that all 32 bits can be used, but the IP block is reused
134 in a lot of designs, some using all 32 bits, some using 18 and some using
135 12. In this case, setting "ngpios = <18>;" informs the driver that only the
136 first 18 GPIOs, at local offset 0 .. 17, are in use.
138 If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
139 additional set of tuples is needed to specify which GPIOs are unusable, with
140 the gpio-reserved-ranges binding. This property indicates the start and size
141 of the GPIOs that can't be used.
143 Optionally, a GPIO controller may have a "gpio-line-names" property. This is
144 an array of strings defining the names of the GPIO lines going out of the
145 GPIO controller. This name should be the most meaningful producer name
146 for the system, such as a rail name indicating the usage. Package names
147 such as pin name are discouraged: such lines have opaque names (since they
148 are by definition generic purpose) and such names are usually not very
149 helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
150 reasonable line names as they describe what the line is used for. "GPIO0"
151 is not a good name to give to a GPIO line. Placeholders are discouraged:
152 rather use the "" (blank string) if the use of the GPIO line is undefined
153 in your design. The names are assigned starting from line offset 0 from
154 left to right from the passed array. An incomplete array (where the number
155 of passed named are less than ngpios) will still be used up until the last
156 provided valid line index.
160 gpio-controller@00000000 {
162 reg = <0x00000000 0x1000>;
166 gpio-reserved-ranges = <0 4>, <12 2>;
167 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
168 "LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
169 "Row A", "Row B", "Row C", "Row D", "NMI button",
173 The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
174 providing automatic GPIO request and configuration as part of the
175 gpio-controller's driver probe function.
177 Each GPIO hog definition is represented as a child node of the GPIO controller.
179 - gpio-hog: A property specifying that this child node represents a GPIO hog.
180 - gpios: Store the GPIO information (id, flags, ...) for each GPIO to
181 affect. Shall contain an integer multiple of the number of cells
182 specified in its parent node (GPIO controller node).
183 Only one of the following properties scanned in the order shown below.
184 This means that when multiple properties are present they will be searched
185 in the order presented below and the first match is taken as the intended
187 - input: A property specifying to set the GPIO direction as input.
188 - output-low A property specifying to set the GPIO direction as output with
190 - output-high A property specifying to set the GPIO direction as output with
194 - line-name: The GPIO label name. If not present the node name is used.
196 Example of two SOC GPIO banks defined as gpio-controller nodes:
198 qe_pio_a: gpio-controller@1400 {
199 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
208 line-name = "foo-bar-gpio";
212 qe_pio_e: gpio-controller@1460 {
213 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
219 2.1) gpio- and pin-controller interaction
220 -----------------------------------------
222 Some or all of the GPIOs provided by a GPIO controller may be routed to pins
223 on the package via a pin controller. This allows muxing those pins between
224 GPIO and other functions. It is a fairly common practice among silicon
227 2.2) Ordinary (numerical) GPIO ranges
228 -------------------------------------
230 It is useful to represent which GPIOs correspond to which pins on which pin
231 controllers. The gpio-ranges property described below represents this with
232 a discrete set of ranges mapping pins from the pin controller local number space
233 to pins in the GPIO controller local number space.
235 The format is: <[pin controller phandle], [GPIO controller offset],
236 [pin controller offset], [number of pins]>;
238 The GPIO controller offset pertains to the GPIO controller node containing the
241 The pin controller node referenced by the phandle must conform to the bindings
242 described in pinctrl/pinctrl-bindings.txt.
244 Each offset runs from 0 to N. It is perfectly fine to pile any number of
245 ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but
246 in practice these ranges are often lumped in discrete sets.
250 gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;
253 - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and
254 - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29
259 qe_pio_e: gpio-controller@1460 {
261 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
264 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
267 Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
268 pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
272 2.3) GPIO ranges from named pin groups
273 --------------------------------------
275 It is also possible to use pin groups for gpio ranges when pin groups are the
276 easiest and most convenient mapping.
278 Both both <pinctrl-base> and <count> must set to 0 when using named pin groups
281 The property gpio-ranges-group-names must contain exactly one string for each
284 Elements of gpio-ranges-group-names must contain the name of a pin group
285 defined in the respective pin controller. The number of pins/GPIO lines in the
286 range is the number of pins in that pin group. The number of pins of that
287 group is defined int the implementation and not in the device tree.
289 If numerical and named pin groups are mixed, the string corresponding to a
290 numerical pin range in gpio-ranges-group-names must be empty.
294 gpio_pio_i: gpio-controller@14b0 {
296 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
299 gpio-ranges = <&pinctrl1 0 20 10>,
303 gpio-ranges-group-names = "",
309 Here, three GPIO ranges are defined referring to two pin controllers.
311 pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges
312 in pinctrl2 are defined using the pin groups named "foo" and "bar".
314 Previous versions of this binding required all pin controller nodes that
315 were referenced by any gpio-ranges property to contain a property named
316 #gpio-range-cells with value <3>. This requirement is now deprecated.
317 However, that property may still exist in older device trees for
318 compatibility reasons, and would still be required even in new device
319 trees that need to be compatible with older software.