Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

   1 * Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
   2
   3 Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
   4 controller instances named DMAC capable of serving multiple clients. Channels
   5 can be dedicated to specific clients or shared between a large number of
   6 clients.
   7
   8 Each DMA client is connected to one dedicated port of the DMAC, identified by
   9 an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
  10 256 clients in total. When the number of hardware channels is lower than the
  11 number of clients to be served, channels must be shared between multiple DMA
  12 clients. The association of DMA clients to DMAC channels is fully dynamic and
  13 not described in these device tree bindings.
  14
  15 Required Properties:
  16
  17 - compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
  18               Examples with soctypes are:
  19                 - "renesas,dmac-r8a7743" (RZ/G1M)
  20                 - "renesas,dmac-r8a7744" (RZ/G1N)
  21                 - "renesas,dmac-r8a7745" (RZ/G1E)
  22                 - "renesas,dmac-r8a77470" (RZ/G1C)
  23                 - "renesas,dmac-r8a7790" (R-Car H2)
  24                 - "renesas,dmac-r8a7791" (R-Car M2-W)
  25                 - "renesas,dmac-r8a7792" (R-Car V2H)
  26                 - "renesas,dmac-r8a7793" (R-Car M2-N)
  27                 - "renesas,dmac-r8a7794" (R-Car E2)
  28                 - "renesas,dmac-r8a7795" (R-Car H3)
  29                 - "renesas,dmac-r8a7796" (R-Car M3-W)
  30                 - "renesas,dmac-r8a77965" (R-Car M3-N)
  31                 - "renesas,dmac-r8a77970" (R-Car V3M)
  32                 - "renesas,dmac-r8a77980" (R-Car V3H)
  33                 - "renesas,dmac-r8a77990" (R-Car E3)
  34                 - "renesas,dmac-r8a77995" (R-Car D3)
  35
  36 - reg: base address and length of the registers block for the DMAC
  37
  38 - interrupts: interrupt specifiers for the DMAC, one for each entry in
  39   interrupt-names.
  40 - interrupt-names: one entry for the error interrupt, named "error", plus one
  41   entry per channel, named "ch%u", where %u is the channel number ranging from
  42   zero to the number of channels minus one.
  43
  44 - clock-names: "fck" for the functional clock
  45 - clocks: a list of phandle + clock-specifier pairs, one for each entry
  46   in clock-names.
  47 - clock-names: must contain "fck" for the functional clock.
  48
  49 - #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
  50   connected to the DMA client
  51 - dma-channels: number of DMA channels
  52
  53 Example: R8A7790 (R-Car H2) SYS-DMACs
  54
  55         dmac0: dma-controller@e6700000 {
  56                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
  57                 reg = <0 0xe6700000 0 0x20000>;
  58                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
  59                               0 200 IRQ_TYPE_LEVEL_HIGH
  60                               0 201 IRQ_TYPE_LEVEL_HIGH
  61                               0 202 IRQ_TYPE_LEVEL_HIGH
  62                               0 203 IRQ_TYPE_LEVEL_HIGH
  63                               0 204 IRQ_TYPE_LEVEL_HIGH
  64                               0 205 IRQ_TYPE_LEVEL_HIGH
  65                               0 206 IRQ_TYPE_LEVEL_HIGH
  66                               0 207 IRQ_TYPE_LEVEL_HIGH
  67                               0 208 IRQ_TYPE_LEVEL_HIGH
  68                               0 209 IRQ_TYPE_LEVEL_HIGH
  69                               0 210 IRQ_TYPE_LEVEL_HIGH
  70                               0 211 IRQ_TYPE_LEVEL_HIGH
  71                               0 212 IRQ_TYPE_LEVEL_HIGH
  72                               0 213 IRQ_TYPE_LEVEL_HIGH
  73                               0 214 IRQ_TYPE_LEVEL_HIGH>;
  74                 interrupt-names = "error",
  75                                 "ch0", "ch1", "ch2", "ch3",
  76                                 "ch4", "ch5", "ch6", "ch7",
  77                                 "ch8", "ch9", "ch10", "ch11",
  78                                 "ch12", "ch13", "ch14";
  79                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
  80                 clock-names = "fck";
  81                 #dma-cells = <1>;
  82                 dma-channels = <15>;
  83         };
  84
  85         dmac1: dma-controller@e6720000 {
  86                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
  87                 reg = <0 0xe6720000 0 0x20000>;
  88                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
  89                               0 216 IRQ_TYPE_LEVEL_HIGH
  90                               0 217 IRQ_TYPE_LEVEL_HIGH
  91                               0 218 IRQ_TYPE_LEVEL_HIGH
  92                               0 219 IRQ_TYPE_LEVEL_HIGH
  93                               0 308 IRQ_TYPE_LEVEL_HIGH
  94                               0 309 IRQ_TYPE_LEVEL_HIGH
  95                               0 310 IRQ_TYPE_LEVEL_HIGH
  96                               0 311 IRQ_TYPE_LEVEL_HIGH
  97                               0 312 IRQ_TYPE_LEVEL_HIGH
  98                               0 313 IRQ_TYPE_LEVEL_HIGH
  99                               0 314 IRQ_TYPE_LEVEL_HIGH
 100                               0 315 IRQ_TYPE_LEVEL_HIGH
 101                               0 316 IRQ_TYPE_LEVEL_HIGH
 102                               0 317 IRQ_TYPE_LEVEL_HIGH
 103                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 104                 interrupt-names = "error",
 105                                 "ch0", "ch1", "ch2", "ch3",
 106                                 "ch4", "ch5", "ch6", "ch7",
 107                                 "ch8", "ch9", "ch10", "ch11",
 108                                 "ch12", "ch13", "ch14";
 109                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 110                 clock-names = "fck";
 111                 #dma-cells = <1>;
 112                 dma-channels = <15>;
 113         };