Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt

   1 * Renesas R-Car (RZ/G) DMA Controller Device Tree bindings
   2
   3 Renesas R-Car (Gen 2/3) and RZ/G SoCs have multiple multi-channel DMA
   4 controller instances named DMAC capable of serving multiple clients. Channels
   5 can be dedicated to specific clients or shared between a large number of
   6 clients.
   7
   8 Each DMA client is connected to one dedicated port of the DMAC, identified by
   9 an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
  10 256 clients in total. When the number of hardware channels is lower than the
  11 number of clients to be served, channels must be shared between multiple DMA
  12 clients. The association of DMA clients to DMAC channels is fully dynamic and
  13 not described in these device tree bindings.
  14
  15 Required Properties:
  16
  17 - compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
  18               Examples with soctypes are:
  19                 - "renesas,dmac-r8a7743" (RZ/G1M)
  20                 - "renesas,dmac-r8a7744" (RZ/G1N)
  21                 - "renesas,dmac-r8a7745" (RZ/G1E)
  22                 - "renesas,dmac-r8a77470" (RZ/G1C)
  23                 - "renesas,dmac-r8a774a1" (RZ/G2M)
  24                 - "renesas,dmac-r8a774c0" (RZ/G2E)
  25                 - "renesas,dmac-r8a7790" (R-Car H2)
  26                 - "renesas,dmac-r8a7791" (R-Car M2-W)
  27                 - "renesas,dmac-r8a7792" (R-Car V2H)
  28                 - "renesas,dmac-r8a7793" (R-Car M2-N)
  29                 - "renesas,dmac-r8a7794" (R-Car E2)
  30                 - "renesas,dmac-r8a7795" (R-Car H3)
  31                 - "renesas,dmac-r8a7796" (R-Car M3-W)
  32                 - "renesas,dmac-r8a77965" (R-Car M3-N)
  33                 - "renesas,dmac-r8a77970" (R-Car V3M)
  34                 - "renesas,dmac-r8a77980" (R-Car V3H)
  35                 - "renesas,dmac-r8a77990" (R-Car E3)
  36                 - "renesas,dmac-r8a77995" (R-Car D3)
  37
  38 - reg: base address and length of the registers block for the DMAC
  39
  40 - interrupts: interrupt specifiers for the DMAC, one for each entry in
  41   interrupt-names.
  42 - interrupt-names: one entry for the error interrupt, named "error", plus one
  43   entry per channel, named "ch%u", where %u is the channel number ranging from
  44   zero to the number of channels minus one.
  45
  46 - clock-names: "fck" for the functional clock
  47 - clocks: a list of phandle + clock-specifier pairs, one for each entry
  48   in clock-names.
  49 - clock-names: must contain "fck" for the functional clock.
  50
  51 - #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
  52   connected to the DMA client
  53 - dma-channels: number of DMA channels
  54
  55 Example: R8A7790 (R-Car H2) SYS-DMACs
  56
  57         dmac0: dma-controller@e6700000 {
  58                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
  59                 reg = <0 0xe6700000 0 0x20000>;
  60                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
  61                               0 200 IRQ_TYPE_LEVEL_HIGH
  62                               0 201 IRQ_TYPE_LEVEL_HIGH
  63                               0 202 IRQ_TYPE_LEVEL_HIGH
  64                               0 203 IRQ_TYPE_LEVEL_HIGH
  65                               0 204 IRQ_TYPE_LEVEL_HIGH
  66                               0 205 IRQ_TYPE_LEVEL_HIGH
  67                               0 206 IRQ_TYPE_LEVEL_HIGH
  68                               0 207 IRQ_TYPE_LEVEL_HIGH
  69                               0 208 IRQ_TYPE_LEVEL_HIGH
  70                               0 209 IRQ_TYPE_LEVEL_HIGH
  71                               0 210 IRQ_TYPE_LEVEL_HIGH
  72                               0 211 IRQ_TYPE_LEVEL_HIGH
  73                               0 212 IRQ_TYPE_LEVEL_HIGH
  74                               0 213 IRQ_TYPE_LEVEL_HIGH
  75                               0 214 IRQ_TYPE_LEVEL_HIGH>;
  76                 interrupt-names = "error",
  77                                 "ch0", "ch1", "ch2", "ch3",
  78                                 "ch4", "ch5", "ch6", "ch7",
  79                                 "ch8", "ch9", "ch10", "ch11",
  80                                 "ch12", "ch13", "ch14";
  81                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
  82                 clock-names = "fck";
  83                 #dma-cells = <1>;
  84                 dma-channels = <15>;
  85         };
  86
  87         dmac1: dma-controller@e6720000 {
  88                 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
  89                 reg = <0 0xe6720000 0 0x20000>;
  90                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
  91                               0 216 IRQ_TYPE_LEVEL_HIGH
  92                               0 217 IRQ_TYPE_LEVEL_HIGH
  93                               0 218 IRQ_TYPE_LEVEL_HIGH
  94                               0 219 IRQ_TYPE_LEVEL_HIGH
  95                               0 308 IRQ_TYPE_LEVEL_HIGH
  96                               0 309 IRQ_TYPE_LEVEL_HIGH
  97                               0 310 IRQ_TYPE_LEVEL_HIGH
  98                               0 311 IRQ_TYPE_LEVEL_HIGH
  99                               0 312 IRQ_TYPE_LEVEL_HIGH
 100                               0 313 IRQ_TYPE_LEVEL_HIGH
 101                               0 314 IRQ_TYPE_LEVEL_HIGH
 102                               0 315 IRQ_TYPE_LEVEL_HIGH
 103                               0 316 IRQ_TYPE_LEVEL_HIGH
 104                               0 317 IRQ_TYPE_LEVEL_HIGH
 105                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 106                 interrupt-names = "error",
 107                                 "ch0", "ch1", "ch2", "ch3",
 108                                 "ch4", "ch5", "ch6", "ch7",
 109                                 "ch8", "ch9", "ch10", "ch11",
 110                                 "ch12", "ch13", "ch14";
 111                 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
 112                 clock-names = "fck";
 113                 #dma-cells = <1>;
 114                 dma-channels = <15>;
 115         };