1 * Mediatek UART APDMA Controller
4 - compatible should contain:
5 * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
6 * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
8 - reg: The base address of the APDMA register bank.
10 - interrupts: A single interrupt specifier.
12 - clocks : Must contain an entry for each entry in clock-names.
13 See ../clocks/clock-bindings.txt for details.
14 - clock-names: The APDMA clock for register accesses
18 apdma: dma-controller@11000380 {
19 compatible = "mediatek,mt2712-uart-dma";
20 reg = <0 0x11000380 0 0x400>;
21 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_LOW>,
22 <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>,
23 <GIC_SPI 65 IRQ_TYPE_LEVEL_LOW>,
24 <GIC_SPI 66 IRQ_TYPE_LEVEL_LOW>,
25 <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>,
26 <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>,
27 <GIC_SPI 69 IRQ_TYPE_LEVEL_LOW>,
28 <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
29 clocks = <&pericfg CLK_PERI_AP_DMA>;
30 clock-names = "apdma";