4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
12 in the host1x address space. Should be 1.
13 - #size-cells: The number of cells used to represent the size of an address
14 range in the host1x address space. Should be 1.
15 - ranges: The mapping of the host1x address space to the CPU address space.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
19 See ../reset/reset.txt for details.
20 - reset-names: Must include the following entries:
23 The host1x top-level node defines a number of children, each representing one
24 of the following host1x client modules:
29 - compatible: "nvidia,tegra<chip>-mpe"
30 - reg: Physical base address and length of the controller's registers.
31 - interrupts: The interrupt outputs from the controller.
32 - clocks: Must contain one entry, for the module clock.
33 See ../clocks/clock-bindings.txt for details.
34 - resets: Must contain an entry for each entry in reset-names.
35 See ../reset/reset.txt for details.
36 - reset-names: Must include the following entries:
42 - compatible: "nvidia,tegra<chip>-vi"
43 - reg: Physical base address and length of the controller's registers.
44 - interrupts: The interrupt outputs from the controller.
45 - clocks: Must contain one entry, for the module clock.
46 See ../clocks/clock-bindings.txt for details.
47 - resets: Must contain an entry for each entry in reset-names.
48 See ../reset/reset.txt for details.
49 - reset-names: Must include the following entries:
52 - epp: encoder pre-processor
55 - compatible: "nvidia,tegra<chip>-epp"
56 - reg: Physical base address and length of the controller's registers.
57 - interrupts: The interrupt outputs from the controller.
58 - clocks: Must contain one entry, for the module clock.
59 See ../clocks/clock-bindings.txt for details.
60 - resets: Must contain an entry for each entry in reset-names.
61 See ../reset/reset.txt for details.
62 - reset-names: Must include the following entries:
65 - isp: image signal processor
68 - compatible: "nvidia,tegra<chip>-isp"
69 - reg: Physical base address and length of the controller's registers.
70 - interrupts: The interrupt outputs from the controller.
71 - clocks: Must contain one entry, for the module clock.
72 See ../clocks/clock-bindings.txt for details.
73 - resets: Must contain an entry for each entry in reset-names.
74 See ../reset/reset.txt for details.
75 - reset-names: Must include the following entries:
78 - gr2d: 2D graphics engine
81 - compatible: "nvidia,tegra<chip>-gr2d"
82 - reg: Physical base address and length of the controller's registers.
83 - interrupts: The interrupt outputs from the controller.
84 - clocks: Must contain one entry, for the module clock.
85 See ../clocks/clock-bindings.txt for details.
86 - resets: Must contain an entry for each entry in reset-names.
87 See ../reset/reset.txt for details.
88 - reset-names: Must include the following entries:
91 - gr3d: 3D graphics engine
94 - compatible: "nvidia,tegra<chip>-gr3d"
95 - reg: Physical base address and length of the controller's registers.
96 - clocks: Must contain an entry for each entry in clock-names.
97 See ../clocks/clock-bindings.txt for details.
98 - clock-names: Must include the following entries:
99 (This property may be omitted if the only clock in the list is "3d")
101 This MUST be the first entry.
102 - 3d2 (Only required on SoCs with two 3D clocks)
103 - resets: Must contain an entry for each entry in reset-names.
104 See ../reset/reset.txt for details.
105 - reset-names: Must include the following entries:
107 - 3d2 (Only required on SoCs with two 3D clocks)
109 - dc: display controller
112 - compatible: "nvidia,tegra<chip>-dc"
113 - reg: Physical base address and length of the controller's registers.
114 - interrupts: The interrupt outputs from the controller.
115 - clocks: Must contain an entry for each entry in clock-names.
116 See ../clocks/clock-bindings.txt for details.
117 - clock-names: Must include the following entries:
119 This MUST be the first entry.
121 - resets: Must contain an entry for each entry in reset-names.
122 See ../reset/reset.txt for details.
123 - reset-names: Must include the following entries:
125 - nvidia,head: The number of the display controller head. This is used to
126 setup the various types of output to receive video data from the given
129 Each display controller node has a child node, named "rgb", that represents
130 the RGB output associated with the controller. It can take the following
132 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
133 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
134 - nvidia,edid: supplies a binary EDID blob
135 - nvidia,panel: phandle of a display panel
137 - hdmi: High Definition Multimedia Interface
140 - compatible: "nvidia,tegra<chip>-hdmi"
141 - reg: Physical base address and length of the controller's registers.
142 - interrupts: The interrupt outputs from the controller.
143 - hdmi-supply: supply for the +5V HDMI connector pin
144 - vdd-supply: regulator for supply voltage
145 - pll-supply: regulator for PLL
146 - clocks: Must contain an entry for each entry in clock-names.
147 See ../clocks/clock-bindings.txt for details.
148 - clock-names: Must include the following entries:
150 This MUST be the first entry.
152 - resets: Must contain an entry for each entry in reset-names.
153 See ../reset/reset.txt for details.
154 - reset-names: Must include the following entries:
158 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
159 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
160 - nvidia,edid: supplies a binary EDID blob
161 - nvidia,panel: phandle of a display panel
163 - tvo: TV encoder output
166 - compatible: "nvidia,tegra<chip>-tvo"
167 - reg: Physical base address and length of the controller's registers.
168 - interrupts: The interrupt outputs from the controller.
169 - clocks: Must contain one entry, for the module clock.
170 See ../clocks/clock-bindings.txt for details.
172 - dsi: display serial interface
175 - compatible: "nvidia,tegra<chip>-dsi"
176 - reg: Physical base address and length of the controller's registers.
177 - clocks: Must contain an entry for each entry in clock-names.
178 See ../clocks/clock-bindings.txt for details.
179 - clock-names: Must include the following entries:
181 This MUST be the first entry.
184 - resets: Must contain an entry for each entry in reset-names.
185 See ../reset/reset.txt for details.
186 - reset-names: Must include the following entries:
188 - avdd-dsi-supply: phandle of a supply that powers the DSI controller
189 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
190 which pads are used by this DSI output and need to be calibrated. See also
191 ../display/tegra/nvidia,tegra114-mipi.txt.
194 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
195 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
196 - nvidia,edid: supplies a binary EDID blob
197 - nvidia,panel: phandle of a display panel
198 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
199 up with in order to support up to 8 data lanes
201 - sor: serial output resource
204 - compatible: Should be:
205 - "nvidia,tegra124-sor": for Tegra124 and Tegra132
206 - "nvidia,tegra132-sor": for Tegra132
207 - "nvidia,tegra210-sor": for Tegra210
208 - "nvidia,tegra210-sor1": for Tegra210
209 - reg: Physical base address and length of the controller's registers.
210 - interrupts: The interrupt outputs from the controller.
211 - clocks: Must contain an entry for each entry in clock-names.
212 See ../clocks/clock-bindings.txt for details.
213 - clock-names: Must include the following entries:
214 - sor: clock input for the SOR hardware
215 - source: source clock for the SOR clock
216 - parent: input for the pixel clock
217 - dp: reference clock for the SOR clock
218 - safe: safe reference for the SOR clock during power up
219 - resets: Must contain an entry for each entry in reset-names.
220 See ../reset/reset.txt for details.
221 - reset-names: Must include the following entries:
225 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
226 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
227 - nvidia,edid: supplies a binary EDID blob
228 - nvidia,panel: phandle of a display panel
230 Optional properties when driving an eDP output:
231 - nvidia,dpaux: phandle to a DispayPort AUX interface
233 - dpaux: DisplayPort AUX interface
234 - compatible : Should contain one of the following:
235 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
236 - "nvidia,tegra210-dpaux": for Tegra210
237 - reg: Physical base address and length of the controller's registers.
238 - interrupts: The interrupt outputs from the controller.
239 - clocks: Must contain an entry for each entry in clock-names.
240 See ../clocks/clock-bindings.txt for details.
241 - clock-names: Must include the following entries:
242 - dpaux: clock input for the DPAUX hardware
243 - parent: reference clock
244 - resets: Must contain an entry for each entry in reset-names.
245 See ../reset/reset.txt for details.
246 - reset-names: Must include the following entries:
248 - vdd-supply: phandle of a supply that powers the DisplayPort link
249 - i2c-bus: Subnode where I2C slave devices are listed. This subnode
250 must be always present. If there are no I2C slave devices, an empty
251 node should be added. See ../../i2c/i2c.txt for more information.
253 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
254 regarding the DPAUX pad controller bindings.
256 - vic: Video Image Compositor
257 - compatible : "nvidia,tegra<chip>-vic"
258 - reg: Physical base address and length of the controller's registers.
259 - interrupts: The interrupt outputs from the controller.
260 - clocks: Must contain an entry for each entry in clock-names.
261 See ../clocks/clock-bindings.txt for details.
262 - clock-names: Must include the following entries:
263 - vic: clock input for the VIC hardware
264 - resets: Must contain an entry for each entry in reset-names.
265 See ../reset/reset.txt for details.
266 - reset-names: Must include the following entries:
275 compatible = "nvidia,tegra20-host1x", "simple-bus";
276 reg = <0x50000000 0x00024000>;
277 interrupts = <0 65 0x04 /* mpcore syncpt */
278 0 67 0x04>; /* mpcore general */
279 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
280 resets = <&tegra_car 28>;
281 reset-names = "host1x";
283 #address-cells = <1>;
286 ranges = <0x54000000 0x54000000 0x04000000>;
289 compatible = "nvidia,tegra20-mpe";
290 reg = <0x54040000 0x00040000>;
291 interrupts = <0 68 0x04>;
292 clocks = <&tegra_car TEGRA20_CLK_MPE>;
293 resets = <&tegra_car 60>;
298 compatible = "nvidia,tegra20-vi";
299 reg = <0x54080000 0x00040000>;
300 interrupts = <0 69 0x04>;
301 clocks = <&tegra_car TEGRA20_CLK_VI>;
302 resets = <&tegra_car 100>;
307 compatible = "nvidia,tegra20-epp";
308 reg = <0x540c0000 0x00040000>;
309 interrupts = <0 70 0x04>;
310 clocks = <&tegra_car TEGRA20_CLK_EPP>;
311 resets = <&tegra_car 19>;
316 compatible = "nvidia,tegra20-isp";
317 reg = <0x54100000 0x00040000>;
318 interrupts = <0 71 0x04>;
319 clocks = <&tegra_car TEGRA20_CLK_ISP>;
320 resets = <&tegra_car 23>;
325 compatible = "nvidia,tegra20-gr2d";
326 reg = <0x54140000 0x00040000>;
327 interrupts = <0 72 0x04>;
328 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
329 resets = <&tegra_car 21>;
334 compatible = "nvidia,tegra20-gr3d";
335 reg = <0x54180000 0x00040000>;
336 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
337 resets = <&tegra_car 24>;
342 compatible = "nvidia,tegra20-dc";
343 reg = <0x54200000 0x00040000>;
344 interrupts = <0 73 0x04>;
345 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
346 <&tegra_car TEGRA20_CLK_PLL_P>;
347 clock-names = "dc", "parent";
348 resets = <&tegra_car 27>;
357 compatible = "nvidia,tegra20-dc";
358 reg = <0x54240000 0x00040000>;
359 interrupts = <0 74 0x04>;
360 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
361 <&tegra_car TEGRA20_CLK_PLL_P>;
362 clock-names = "dc", "parent";
363 resets = <&tegra_car 26>;
372 compatible = "nvidia,tegra20-hdmi";
373 reg = <0x54280000 0x00040000>;
374 interrupts = <0 75 0x04>;
375 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
376 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
377 clock-names = "hdmi", "parent";
378 resets = <&tegra_car 51>;
379 reset-names = "hdmi";
384 compatible = "nvidia,tegra20-tvo";
385 reg = <0x542c0000 0x00040000>;
386 interrupts = <0 76 0x04>;
387 clocks = <&tegra_car TEGRA20_CLK_TVO>;
392 compatible = "nvidia,tegra20-dsi";
393 reg = <0x54300000 0x00040000>;
394 clocks = <&tegra_car TEGRA20_CLK_DSI>,
395 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
396 clock-names = "dsi", "parent";
397 resets = <&tegra_car 48>;