Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt

   1 Allwinner A31 DSI Encoder
   2 =========================
   3
   4 The DSI pipeline consists of two separate blocks: the DSI controller
   5 itself, and its associated D-PHY.
   6
   7 DSI Encoder
   8 -----------
   9
  10 The DSI Encoder generates the DSI signal from the TCON's.
  11
  12 Required properties:
  13   - compatible: value must be one of:
  14     * allwinner,sun6i-a31-mipi-dsi
  15   - reg: base address and size of memory-mapped region
  16   - interrupts: interrupt associated to this IP
  17   - clocks: phandles to the clocks feeding the DSI encoder
  18     * bus: the DSI interface clock
  19     * mod: the DSI module clock
  20   - clock-names: the clock names mentioned above
  21   - phys: phandle to the D-PHY
  22   - phy-names: must be "dphy"
  23   - resets: phandle to the reset controller driving the encoder
  24
  25   - ports: A ports node with endpoint definitions as defined in
  26     Documentation/devicetree/bindings/media/video-interfaces.txt. The
  27     first port should be the input endpoint, usually coming from the
  28     associated TCON.
  29
  30 Any MIPI-DSI device attached to this should be described according to
  31 the bindings defined in ../mipi-dsi-bus.txt
  32
  33 D-PHY
  34 -----
  35
  36 Required properties:
  37   - compatible: value must be one of:
  38     * allwinner,sun6i-a31-mipi-dphy
  39   - reg: base address and size of memory-mapped region
  40   - clocks: phandles to the clocks feeding the DSI encoder
  41     * bus: the DSI interface clock
  42     * mod: the DSI module clock
  43   - clock-names: the clock names mentioned above
  44   - resets: phandle to the reset controller driving the encoder
  45
  46 Example:
  47
  48 dsi0: dsi@1ca0000 {
  49         compatible = "allwinner,sun6i-a31-mipi-dsi";
  50         reg = <0x01ca0000 0x1000>;
  51         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  52         clocks = <&ccu CLK_BUS_MIPI_DSI>,
  53                  <&ccu CLK_DSI_SCLK>;
  54         clock-names = "bus", "mod";
  55         resets = <&ccu RST_BUS_MIPI_DSI>;
  56         phys = <&dphy0>;
  57         phy-names = "dphy";
  58         #address-cells = <1>;
  59         #size-cells = <0>;
  60
  61         panel@0 {
  62                 compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
  63                 reg = <0>;
  64                 power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
  65                 reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
  66                 backlight = <&pwm_bl>;
  67         };
  68
  69         ports {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 port@0 {
  74                         #address-cells = <1>;
  75                         #size-cells = <0>;
  76                         reg = <0>;
  77
  78                         dsi0_in_tcon0: endpoint {
  79                                 remote-endpoint = <&tcon0_out_dsi0>;
  80                         };
  81                 };
  82         };
  83 };
  84
  85 dphy0: d-phy@1ca1000 {
  86         compatible = "allwinner,sun6i-a31-mipi-dphy";
  87         reg = <0x01ca1000 0x1000>;
  88         clocks = <&ccu CLK_BUS_MIPI_DSI>,
  89                  <&ccu CLK_DSI_DPHY>;
  90         clock-names = "bus", "mod";
  91         resets = <&ccu RST_BUS_MIPI_DSI>;
  92         #phy-cells = <0>;
  93 };