1 Allwinner A10 Display Pipeline
2 ==============================
4 The Allwinner A10 Display pipeline is composed of several components
5 that are going to be documented below:
7 For all connections between components up to the TCONs in the display
8 pipeline, when there are multiple components of the same type at the
9 same depth, the local endpoint ID must be the same as the remote
10 component's index. For example, if the remote endpoint is Frontend 1,
11 then the local endpoint ID must be 1.
13 Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
14 [1] -- -- [1] [1] -- -- [1]
18 [0] -- -- [0] [0] -- -- [0]
19 Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
21 For a two pipeline system such as the one depicted above, the lines
22 represent the connections between the components, while the numbers
23 within the square brackets corresponds to the ID of the local endpoint.
25 The same rule also applies to DE 2.0 mixer-TCON connections:
27 Mixer 0 [0] ----------- [0] TCON 0
33 Mixer 1 [1] ----------- [1] TCON 1
38 The HDMI Encoder supports the HDMI video and audio outputs, and does
39 CEC. It is one end of the pipeline.
42 - compatible: value must be one of:
43 * allwinner,sun4i-a10-hdmi
44 * allwinner,sun5i-a10s-hdmi
45 * allwinner,sun6i-a31-hdmi
46 - reg: base address and size of memory-mapped region
47 - interrupts: interrupt associated to this IP
48 - clocks: phandles to the clocks feeding the HDMI encoder
49 * ahb: the HDMI interface clock
50 * mod: the HDMI module clock
51 * ddc: the HDMI ddc clock (A31 only)
52 * pll-0: the first video PLL
53 * pll-1: the second video PLL
54 - clock-names: the clock names mentioned above
55 - resets: phandle to the reset control for the HDMI encoder (A31 only)
56 - dmas: phandles to the DMA channels used by the HDMI encoder
57 * ddc-tx: The channel for DDC transmission
58 * ddc-rx: The channel for DDC reception
59 * audio-tx: The channel used for audio transmission
60 - dma-names: the channel names mentioned above
62 - ports: A ports node with endpoint definitions as defined in
63 Documentation/devicetree/bindings/media/video-interfaces.txt. The
64 first port should be the input endpoint. The second should be the
65 output, usually to an HDMI connector.
70 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
71 with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
73 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
74 Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
75 following device-specific properties.
79 - compatible: value must be one of:
80 * "allwinner,sun8i-a83t-dw-hdmi"
81 * "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"
82 - reg: base address and size of memory-mapped region
83 - reg-io-width: See dw_hdmi.txt. Shall be 1.
84 - interrupts: HDMI interrupt number
85 - clocks: phandles to the clocks feeding the HDMI encoder
86 * iahb: the HDMI bus clock
87 * isfr: the HDMI register clock
89 - clock-names: the clock names mentioned above
90 - resets: phandle to the reset controller
91 - reset-names: must be "ctrl"
92 - phys: phandle to the DWC HDMI PHY
93 - phy-names: must be "phy"
95 - ports: A ports node with endpoint definitions as defined in
96 Documentation/devicetree/bindings/media/video-interfaces.txt. The
97 first port should be the input endpoint. The second should be the
98 output, usually to an HDMI connector.
101 - hvcc-supply: the VCC power supply of the controller
107 - compatible: value must be one of:
108 * allwinner,sun8i-a83t-hdmi-phy
109 * allwinner,sun8i-h3-hdmi-phy
110 * allwinner,sun8i-r40-hdmi-phy
111 * allwinner,sun50i-a64-hdmi-phy
112 - reg: base address and size of memory-mapped region
113 - clocks: phandles to the clocks feeding the HDMI PHY
114 * bus: the HDMI PHY interface clock
115 * mod: the HDMI PHY module clock
116 - clock-names: the clock names mentioned above
117 - resets: phandle to the reset controller driving the PHY
118 - reset-names: must be "phy"
120 H3, A64 and R40 HDMI PHY require additional clocks:
121 - pll-0: parent of phy clock
122 - pll-1: second possible phy clock parent (A64/R40 only)
127 The TV Encoder supports the composite and VGA output. It is one end of
131 - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
132 - reg: base address and size of memory-mapped region
133 - clocks: the clocks driving the TV encoder
134 - resets: phandle to the reset controller driving the encoder
136 - ports: A ports node with endpoint definitions as defined in
137 Documentation/devicetree/bindings/media/video-interfaces.txt. The
138 first port should be the input endpoint.
143 The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
146 - compatible: value must be either:
147 * allwinner,sun4i-a10-tcon
148 * allwinner,sun5i-a13-tcon
149 * allwinner,sun6i-a31-tcon
150 * allwinner,sun6i-a31s-tcon
151 * allwinner,sun7i-a20-tcon
152 * allwinner,sun8i-a33-tcon
153 * allwinner,sun8i-a83t-tcon-lcd
154 * allwinner,sun8i-a83t-tcon-tv
155 * allwinner,sun8i-r40-tcon-tv
156 * allwinner,sun8i-v3s-tcon
157 * allwinner,sun9i-a80-tcon-lcd
158 * allwinner,sun9i-a80-tcon-tv
159 * "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd"
160 * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv"
161 - reg: base address and size of memory-mapped region
162 - interrupts: interrupt associated to this IP
163 - clocks: phandles to the clocks feeding the TCON.
164 - 'ahb': the interface clocks
165 - 'tcon-ch0': The clock driving the TCON channel 0, if supported
166 - resets: phandles to the reset controllers driving the encoder
167 - "lcd": the reset line for the TCON
168 - "edp": the reset line for the eDP block (A80 only)
170 - clock-names: the clock names mentioned above
171 - reset-names: the reset names mentioned above
172 - clock-output-names: Name of the pixel clock created, if TCON supports
175 - ports: A ports node with endpoint definitions as defined in
176 Documentation/devicetree/bindings/media/video-interfaces.txt. The
177 first port should be the input endpoint, the second one the output
179 The output may have multiple endpoints. TCON can have 1 or 2 channels,
180 usually with the first channel being used for the panels interfaces
181 (RGB, LVDS, etc.), and the second being used for the outputs that
182 require another controller (TV Encoder, HDMI, etc.). The endpoints
183 will take an extra property, allwinner,tcon-channel, to specify the
184 channel the endpoint is associated to. If that property is not
185 present, the endpoint number will be used as the channel number.
187 For TCONs with channel 0, there is one more clock required:
188 - 'tcon-ch0': The clock driving the TCON channel 0
189 For TCONs with channel 1, there is one more clock required:
190 - 'tcon-ch1': The clock driving the TCON channel 1
192 When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found
193 in A13, H3, H5 and V3s SoCs), you need one more reset line:
194 - 'lvds': The reset line driving the LVDS logic
196 And on the A23, A31, A31s and A33, you need one more clock line:
197 - 'lvds-alt': An alternative clock source, separate from the TCON channel 0
198 clock, that can be used to drive the LVDS clock
203 TCON TOPs main purpose is to configure whole display pipeline. It determines
204 relationships between mixers and TCONs, selects source TCON for HDMI, muxes
205 LCD and TV encoder GPIO output, selects TV encoder clock source and contains
206 additional TV TCON and DSI gates.
208 It allows display pipeline to be configured in very different ways:
214 \ / [1] TCON-LCD1 - LCD1/LVDS1
216 / \ [2] TCON-TV0 [0] - TVE0/RGB
220 \ [3] TCON-TV1 [1] - TVE1/RGB
222 Note that both TCON TOP references same physical unit. Both mixers can be
223 connected to any TCON.
226 - compatible: value must be one of:
227 * allwinner,sun8i-r40-tcon-top
228 - reg: base address and size of the memory-mapped region.
229 - clocks: phandle to the clocks feeding the TCON TOP
230 * bus: TCON TOP interface clock
231 * tcon-tv0: TCON TV0 clock
233 * tcon-tv1: TCON TV1 clock
235 * dsi: MIPI DSI clock
236 - clock-names: clock name mentioned above
237 - resets: phandle to the reset line driving the TCON TOP
238 - #clock-cells : must contain 1
239 - clock-output-names: Names of clocks created for TCON TV0 channel clock,
240 TCON TV1 channel clock and DSI channel clock, in that order.
242 - ports: A ports node with endpoint definitions as defined in
243 Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should
245 * port 0 is input for mixer0 mux
246 * port 1 is output for mixer0 mux
247 * port 2 is input for mixer1 mux
248 * port 3 is output for mixer1 mux
249 * port 4 is input for HDMI mux
250 * port 5 is output for HDMI mux
251 All output endpoints for mixer muxes and input endpoints for HDMI mux should
252 have reg property with the id of the target TCON, as shown in above graph
253 (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one
254 endpoint connected to remote endpoint.
259 The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
260 (A31, A23, A33, A80), allows to dynamically adjust pixel
261 brightness/contrast based on histogram measurements for LCD content
262 adaptive backlight control.
266 - compatible: value must be one of:
267 * allwinner,sun6i-a31-drc
268 * allwinner,sun6i-a31s-drc
269 * allwinner,sun8i-a33-drc
270 * allwinner,sun9i-a80-drc
271 - reg: base address and size of the memory-mapped region.
272 - interrupts: interrupt associated to this IP
273 - clocks: phandles to the clocks feeding the DRC
274 * ahb: the DRC interface clock
275 * mod: the DRC module clock
276 * ram: the DRC DRAM clock
277 - clock-names: the clock names mentioned above
278 - resets: phandles to the reset line driving the DRC
280 - ports: A ports node with endpoint definitions as defined in
281 Documentation/devicetree/bindings/media/video-interfaces.txt. The
282 first port should be the input endpoints, the second one the outputs
284 Display Engine Backend
285 ----------------------
287 The display engine backend exposes layers and sprites to the
291 - compatible: value must be one of:
292 * allwinner,sun4i-a10-display-backend
293 * allwinner,sun5i-a13-display-backend
294 * allwinner,sun6i-a31-display-backend
295 * allwinner,sun7i-a20-display-backend
296 * allwinner,sun8i-a33-display-backend
297 * allwinner,sun9i-a80-display-backend
298 - reg: base address and size of the memory-mapped region.
299 - interrupts: interrupt associated to this IP
300 - clocks: phandles to the clocks feeding the frontend and backend
301 * ahb: the backend interface clock
302 * mod: the backend module clock
303 * ram: the backend DRAM clock
304 - clock-names: the clock names mentioned above
305 - resets: phandles to the reset controllers driving the backend
307 - ports: A ports node with endpoint definitions as defined in
308 Documentation/devicetree/bindings/media/video-interfaces.txt. The
309 first port should be the input endpoints, the second one the output
311 On the A33, some additional properties are required:
312 - reg needs to have an additional region corresponding to the SAT
313 - reg-names need to be set, with "be" and "sat"
314 - clocks and clock-names need to have a phandle to the SAT bus
315 clocks, whose name will be "sat"
316 - resets and reset-names need to have a phandle to the SAT bus
317 resets, whose name will be "sat"
322 The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
323 can sharpen the display content in both luma and chroma channels.
326 - compatible: value must be one of:
327 * allwinner,sun9i-a80-deu
328 - reg: base address and size of the memory-mapped region.
329 - interrupts: interrupt associated to this IP
330 - clocks: phandles to the clocks feeding the DEU
331 * ahb: the DEU interface clock
332 * mod: the DEU module clock
333 * ram: the DEU DRAM clock
334 - clock-names: the clock names mentioned above
335 - resets: phandles to the reset line driving the DEU
337 - ports: A ports node with endpoint definitions as defined in
338 Documentation/devicetree/bindings/media/video-interfaces.txt. The
339 first port should be the input endpoints, the second one the outputs
341 Display Engine Frontend
342 -----------------------
344 The display engine frontend does formats conversion, scaling,
345 deinterlacing and color space conversion.
348 - compatible: value must be one of:
349 * allwinner,sun4i-a10-display-frontend
350 * allwinner,sun5i-a13-display-frontend
351 * allwinner,sun6i-a31-display-frontend
352 * allwinner,sun7i-a20-display-frontend
353 * allwinner,sun8i-a33-display-frontend
354 * allwinner,sun9i-a80-display-frontend
355 - reg: base address and size of the memory-mapped region.
356 - interrupts: interrupt associated to this IP
357 - clocks: phandles to the clocks feeding the frontend and backend
358 * ahb: the backend interface clock
359 * mod: the backend module clock
360 * ram: the backend DRAM clock
361 - clock-names: the clock names mentioned above
362 - resets: phandles to the reset controllers driving the backend
364 - ports: A ports node with endpoint definitions as defined in
365 Documentation/devicetree/bindings/media/video-interfaces.txt. The
366 first port should be the input endpoints, the second one the outputs
368 Display Engine 2.0 Mixer
369 ------------------------
371 The DE2 mixer have many functionalities, currently only layer blending is
375 - compatible: value must be one of:
376 * allwinner,sun8i-a83t-de2-mixer-0
377 * allwinner,sun8i-a83t-de2-mixer-1
378 * allwinner,sun8i-h3-de2-mixer-0
379 * allwinner,sun8i-r40-de2-mixer-0
380 * allwinner,sun8i-r40-de2-mixer-1
381 * allwinner,sun8i-v3s-de2-mixer
382 * allwinner,sun50i-a64-de2-mixer-0
383 * allwinner,sun50i-a64-de2-mixer-1
384 - reg: base address and size of the memory-mapped region.
385 - clocks: phandles to the clocks feeding the mixer
386 * bus: the mixer interface clock
387 * mod: the mixer module clock
388 - clock-names: the clock names mentioned above
389 - resets: phandles to the reset controllers driving the mixer
391 - ports: A ports node with endpoint definitions as defined in
392 Documentation/devicetree/bindings/media/video-interfaces.txt. The
393 first port should be the input endpoints, the second one the output
396 Display Engine Pipeline
397 -----------------------
399 The display engine pipeline (and its entry point, since it can be
400 either directly the backend or the frontend) is represented as an
404 - compatible: value must be one of:
405 * allwinner,sun4i-a10-display-engine
406 * allwinner,sun5i-a10s-display-engine
407 * allwinner,sun5i-a13-display-engine
408 * allwinner,sun6i-a31-display-engine
409 * allwinner,sun6i-a31s-display-engine
410 * allwinner,sun7i-a20-display-engine
411 * allwinner,sun8i-a33-display-engine
412 * allwinner,sun8i-a83t-display-engine
413 * allwinner,sun8i-h3-display-engine
414 * allwinner,sun8i-r40-display-engine
415 * allwinner,sun8i-v3s-display-engine
416 * allwinner,sun9i-a80-display-engine
417 * allwinner,sun50i-a64-display-engine
419 - allwinner,pipelines: list of phandle to the display engine
420 frontends (DE 1.0) or mixers (DE 2.0) available.
425 compatible = "olimex,lcd-olinuxino-43-ts";
426 #address-cells = <1>;
430 #address-cells = <1>;
433 panel_input: endpoint {
434 remote-endpoint = <&tcon0_out_panel>;
440 compatible = "hdmi-connector";
444 hdmi_con_in: endpoint {
445 remote-endpoint = <&hdmi_out_con>;
451 compatible = "allwinner,sun5i-a10s-hdmi";
452 reg = <0x01c16000 0x1000>;
454 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
455 <&ccu CLK_PLL_VIDEO0_2X>,
456 <&ccu CLK_PLL_VIDEO1_2X>;
457 clock-names = "ahb", "mod", "pll-0", "pll-1";
458 dmas = <&dma SUN4I_DMA_NORMAL 16>,
459 <&dma SUN4I_DMA_NORMAL 16>,
460 <&dma SUN4I_DMA_DEDICATED 24>;
461 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
464 #address-cells = <1>;
468 #address-cells = <1>;
472 hdmi_in_tcon0: endpoint {
473 remote-endpoint = <&tcon0_out_hdmi>;
478 #address-cells = <1>;
482 hdmi_out_con: endpoint {
483 remote-endpoint = <&hdmi_con_in>;
489 tve0: tv-encoder@1c0a000 {
490 compatible = "allwinner,sun4i-a10-tv-encoder";
491 reg = <0x01c0a000 0x1000>;
492 clocks = <&ahb_gates 34>;
493 resets = <&tcon_ch0_clk 0>;
496 #address-cells = <1>;
499 tve0_in_tcon0: endpoint@0 {
501 remote-endpoint = <&tcon0_out_tve0>;
506 tcon0: lcd-controller@1c0c000 {
507 compatible = "allwinner,sun5i-a13-tcon";
508 reg = <0x01c0c000 0x1000>;
510 resets = <&tcon_ch0_clk 1>;
512 clocks = <&ahb_gates 36>,
518 clock-output-names = "tcon-pixel-clock";
521 #address-cells = <1>;
525 #address-cells = <1>;
529 tcon0_in_be0: endpoint@0 {
531 remote-endpoint = <&be0_out_tcon0>;
536 #address-cells = <1>;
540 tcon0_out_panel: endpoint@0 {
542 remote-endpoint = <&panel_input>;
545 tcon0_out_tve0: endpoint@1 {
547 remote-endpoint = <&tve0_in_tcon0>;
553 fe0: display-frontend@1e00000 {
554 compatible = "allwinner,sun5i-a13-display-frontend";
555 reg = <0x01e00000 0x20000>;
557 clocks = <&ahb_gates 46>, <&de_fe_clk>,
559 clock-names = "ahb", "mod",
561 resets = <&de_fe_clk>;
564 #address-cells = <1>;
568 #address-cells = <1>;
572 fe0_out_be0: endpoint {
573 remote-endpoint = <&be0_in_fe0>;
579 be0: display-backend@1e60000 {
580 compatible = "allwinner,sun5i-a13-display-backend";
581 reg = <0x01e60000 0x10000>;
583 clocks = <&ahb_gates 44>, <&de_be_clk>,
585 clock-names = "ahb", "mod",
587 resets = <&de_be_clk>;
590 #address-cells = <1>;
594 #address-cells = <1>;
598 be0_in_fe0: endpoint@0 {
600 remote-endpoint = <&fe0_out_be0>;
605 #address-cells = <1>;
609 be0_out_tcon0: endpoint@0 {
611 remote-endpoint = <&tcon0_in_be0>;
618 compatible = "allwinner,sun5i-a13-display-engine";
619 allwinner,pipelines = <&fe0>;