1 Allwinner A10 Display Pipeline
2 ==============================
4 The Allwinner A10 Display pipeline is composed of several components
5 that are going to be documented below:
7 For all connections between components up to the TCONs in the display
8 pipeline, when there are multiple components of the same type at the
9 same depth, the local endpoint ID must be the same as the remote
10 component's index. For example, if the remote endpoint is Frontend 1,
11 then the local endpoint ID must be 1.
13 Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
14 [1] -- -- [1] [1] -- -- [1]
18 [0] -- -- [0] [0] -- -- [0]
19 Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
21 For a two pipeline system such as the one depicted above, the lines
22 represent the connections between the components, while the numbers
23 within the square brackets corresponds to the ID of the local endpoint.
25 The same rule also applies to DE 2.0 mixer-TCON connections:
27 Mixer 0 [0] ----------- [0] TCON 0
33 Mixer 1 [1] ----------- [1] TCON 1
38 The HDMI Encoder supports the HDMI video and audio outputs, and does
39 CEC. It is one end of the pipeline.
42 - compatible: value must be one of:
43 * allwinner,sun4i-a10-hdmi
44 * allwinner,sun5i-a10s-hdmi
45 * allwinner,sun6i-a31-hdmi
46 - reg: base address and size of memory-mapped region
47 - interrupts: interrupt associated to this IP
48 - clocks: phandles to the clocks feeding the HDMI encoder
49 * ahb: the HDMI interface clock
50 * mod: the HDMI module clock
51 * ddc: the HDMI ddc clock (A31 only)
52 * pll-0: the first video PLL
53 * pll-1: the second video PLL
54 - clock-names: the clock names mentioned above
55 - resets: phandle to the reset control for the HDMI encoder (A31 only)
56 - dmas: phandles to the DMA channels used by the HDMI encoder
57 * ddc-tx: The channel for DDC transmission
58 * ddc-rx: The channel for DDC reception
59 * audio-tx: The channel used for audio transmission
60 - dma-names: the channel names mentioned above
62 - ports: A ports node with endpoint definitions as defined in
63 Documentation/devicetree/bindings/media/video-interfaces.txt. The
64 first port should be the input endpoint. The second should be the
65 output, usually to an HDMI connector.
70 The TV Encoder supports the composite and VGA output. It is one end of
74 - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
75 - reg: base address and size of memory-mapped region
76 - clocks: the clocks driving the TV encoder
77 - resets: phandle to the reset controller driving the encoder
79 - ports: A ports node with endpoint definitions as defined in
80 Documentation/devicetree/bindings/media/video-interfaces.txt. The
81 first port should be the input endpoint.
86 The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
89 - compatible: value must be either:
90 * allwinner,sun4i-a10-tcon
91 * allwinner,sun5i-a13-tcon
92 * allwinner,sun6i-a31-tcon
93 * allwinner,sun6i-a31s-tcon
94 * allwinner,sun7i-a20-tcon
95 * allwinner,sun8i-a33-tcon
96 * allwinner,sun8i-v3s-tcon
97 - reg: base address and size of memory-mapped region
98 - interrupts: interrupt associated to this IP
99 - clocks: phandles to the clocks feeding the TCON. Three are needed:
100 - 'ahb': the interface clocks
101 - 'tcon-ch0': The clock driving the TCON channel 0
102 - resets: phandles to the reset controllers driving the encoder
103 - "lcd": the reset line for the TCON channel 0
105 - clock-names: the clock names mentioned above
106 - reset-names: the reset names mentioned above
107 - clock-output-names: Name of the pixel clock created
109 - ports: A ports node with endpoint definitions as defined in
110 Documentation/devicetree/bindings/media/video-interfaces.txt. The
111 first port should be the input endpoint, the second one the output
113 The output may have multiple endpoints. The TCON has two channels,
114 usually with the first channel being used for the panels interfaces
115 (RGB, LVDS, etc.), and the second being used for the outputs that
116 require another controller (TV Encoder, HDMI, etc.). The endpoints
117 will take an extra property, allwinner,tcon-channel, to specify the
118 channel the endpoint is associated to. If that property is not
119 present, the endpoint number will be used as the channel number.
121 On SoCs other than the A33 and V3s, there is one more clock required:
122 - 'tcon-ch1': The clock driving the TCON channel 1
127 The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
128 (A31, A23, A33), allows to dynamically adjust pixel
129 brightness/contrast based on histogram measurements for LCD content
130 adaptive backlight control.
134 - compatible: value must be one of:
135 * allwinner,sun6i-a31-drc
136 * allwinner,sun6i-a31s-drc
137 * allwinner,sun8i-a33-drc
138 - reg: base address and size of the memory-mapped region.
139 - interrupts: interrupt associated to this IP
140 - clocks: phandles to the clocks feeding the DRC
141 * ahb: the DRC interface clock
142 * mod: the DRC module clock
143 * ram: the DRC DRAM clock
144 - clock-names: the clock names mentioned above
145 - resets: phandles to the reset line driving the DRC
147 - ports: A ports node with endpoint definitions as defined in
148 Documentation/devicetree/bindings/media/video-interfaces.txt. The
149 first port should be the input endpoints, the second one the outputs
151 Display Engine Backend
152 ----------------------
154 The display engine backend exposes layers and sprites to the
158 - compatible: value must be one of:
159 * allwinner,sun4i-a10-display-backend
160 * allwinner,sun5i-a13-display-backend
161 * allwinner,sun6i-a31-display-backend
162 * allwinner,sun7i-a20-display-backend
163 * allwinner,sun8i-a33-display-backend
164 - reg: base address and size of the memory-mapped region.
165 - interrupts: interrupt associated to this IP
166 - clocks: phandles to the clocks feeding the frontend and backend
167 * ahb: the backend interface clock
168 * mod: the backend module clock
169 * ram: the backend DRAM clock
170 - clock-names: the clock names mentioned above
171 - resets: phandles to the reset controllers driving the backend
173 - ports: A ports node with endpoint definitions as defined in
174 Documentation/devicetree/bindings/media/video-interfaces.txt. The
175 first port should be the input endpoints, the second one the output
177 On the A33, some additional properties are required:
178 - reg needs to have an additional region corresponding to the SAT
179 - reg-names need to be set, with "be" and "sat"
180 - clocks and clock-names need to have a phandle to the SAT bus
181 clocks, whose name will be "sat"
182 - resets and reset-names need to have a phandle to the SAT bus
183 resets, whose name will be "sat"
185 Display Engine Frontend
186 -----------------------
188 The display engine frontend does formats conversion, scaling,
189 deinterlacing and color space conversion.
192 - compatible: value must be one of:
193 * allwinner,sun4i-a10-display-frontend
194 * allwinner,sun5i-a13-display-frontend
195 * allwinner,sun6i-a31-display-frontend
196 * allwinner,sun7i-a20-display-frontend
197 * allwinner,sun8i-a33-display-frontend
198 - reg: base address and size of the memory-mapped region.
199 - interrupts: interrupt associated to this IP
200 - clocks: phandles to the clocks feeding the frontend and backend
201 * ahb: the backend interface clock
202 * mod: the backend module clock
203 * ram: the backend DRAM clock
204 - clock-names: the clock names mentioned above
205 - resets: phandles to the reset controllers driving the backend
207 - ports: A ports node with endpoint definitions as defined in
208 Documentation/devicetree/bindings/media/video-interfaces.txt. The
209 first port should be the input endpoints, the second one the outputs
211 Display Engine 2.0 Mixer
212 ------------------------
214 The DE2 mixer have many functionalities, currently only layer blending is
218 - compatible: value must be one of:
219 * allwinner,sun8i-v3s-de2-mixer
220 - reg: base address and size of the memory-mapped region.
221 - clocks: phandles to the clocks feeding the mixer
222 * bus: the mixer interface clock
223 * mod: the mixer module clock
224 - clock-names: the clock names mentioned above
225 - resets: phandles to the reset controllers driving the mixer
227 - ports: A ports node with endpoint definitions as defined in
228 Documentation/devicetree/bindings/media/video-interfaces.txt. The
229 first port should be the input endpoints, the second one the output
232 Display Engine Pipeline
233 -----------------------
235 The display engine pipeline (and its entry point, since it can be
236 either directly the backend or the frontend) is represented as an
240 - compatible: value must be one of:
241 * allwinner,sun4i-a10-display-engine
242 * allwinner,sun5i-a10s-display-engine
243 * allwinner,sun5i-a13-display-engine
244 * allwinner,sun6i-a31-display-engine
245 * allwinner,sun6i-a31s-display-engine
246 * allwinner,sun7i-a20-display-engine
247 * allwinner,sun8i-a33-display-engine
248 * allwinner,sun8i-v3s-display-engine
250 - allwinner,pipelines: list of phandle to the display engine
251 frontends (DE 1.0) or mixers (DE 2.0) available.
256 compatible = "olimex,lcd-olinuxino-43-ts";
257 #address-cells = <1>;
261 #address-cells = <1>;
264 panel_input: endpoint {
265 remote-endpoint = <&tcon0_out_panel>;
271 compatible = "hdmi-connector";
275 hdmi_con_in: endpoint {
276 remote-endpoint = <&hdmi_out_con>;
282 compatible = "allwinner,sun5i-a10s-hdmi";
283 reg = <0x01c16000 0x1000>;
285 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
286 <&ccu CLK_PLL_VIDEO0_2X>,
287 <&ccu CLK_PLL_VIDEO1_2X>;
288 clock-names = "ahb", "mod", "pll-0", "pll-1";
289 dmas = <&dma SUN4I_DMA_NORMAL 16>,
290 <&dma SUN4I_DMA_NORMAL 16>,
291 <&dma SUN4I_DMA_DEDICATED 24>;
292 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
295 #address-cells = <1>;
299 #address-cells = <1>;
303 hdmi_in_tcon0: endpoint {
304 remote-endpoint = <&tcon0_out_hdmi>;
309 #address-cells = <1>;
313 hdmi_out_con: endpoint {
314 remote-endpoint = <&hdmi_con_in>;
320 tve0: tv-encoder@1c0a000 {
321 compatible = "allwinner,sun4i-a10-tv-encoder";
322 reg = <0x01c0a000 0x1000>;
323 clocks = <&ahb_gates 34>;
324 resets = <&tcon_ch0_clk 0>;
327 #address-cells = <1>;
330 tve0_in_tcon0: endpoint@0 {
332 remote-endpoint = <&tcon0_out_tve0>;
337 tcon0: lcd-controller@1c0c000 {
338 compatible = "allwinner,sun5i-a13-tcon";
339 reg = <0x01c0c000 0x1000>;
341 resets = <&tcon_ch0_clk 1>;
343 clocks = <&ahb_gates 36>,
349 clock-output-names = "tcon-pixel-clock";
352 #address-cells = <1>;
356 #address-cells = <1>;
360 tcon0_in_be0: endpoint@0 {
362 remote-endpoint = <&be0_out_tcon0>;
367 #address-cells = <1>;
371 tcon0_out_panel: endpoint@0 {
373 remote-endpoint = <&panel_input>;
376 tcon0_out_tve0: endpoint@1 {
378 remote-endpoint = <&tve0_in_tcon0>;
384 fe0: display-frontend@1e00000 {
385 compatible = "allwinner,sun5i-a13-display-frontend";
386 reg = <0x01e00000 0x20000>;
388 clocks = <&ahb_gates 46>, <&de_fe_clk>,
390 clock-names = "ahb", "mod",
392 resets = <&de_fe_clk>;
395 #address-cells = <1>;
399 #address-cells = <1>;
403 fe0_out_be0: endpoint {
404 remote-endpoint = <&be0_in_fe0>;
410 be0: display-backend@1e60000 {
411 compatible = "allwinner,sun5i-a13-display-backend";
412 reg = <0x01e60000 0x10000>;
414 clocks = <&ahb_gates 44>, <&de_be_clk>,
416 clock-names = "ahb", "mod",
418 resets = <&de_be_clk>;
421 #address-cells = <1>;
425 #address-cells = <1>;
429 be0_in_fe0: endpoint@0 {
431 remote-endpoint = <&fe0_out_be0>;
436 #address-cells = <1>;
440 be0_out_tcon0: endpoint@0 {
442 remote-endpoint = <&tcon0_in_be0>;
449 compatible = "allwinner,sun5i-a13-display-engine";
450 allwinner,pipelines = <&fe0>;