Documentation/devicetree/bindings/display/st,stm32-ltdc.txt

   1 * STMicroelectronics STM32 lcd-tft display controller
   2
   3 - ltdc: lcd-tft display controller host
   4   Required properties:
   5   - compatible: "st,stm32-ltdc"
   6   - reg: Physical base address of the IP registers and length of memory mapped region.
   7   - clocks: A list of phandle + clock-specifier pairs, one for each
   8     entry in 'clock-names'.
   9   - clock-names: A list of clock names. For ltdc it should contain:
  10       - "lcd" for the clock feeding the output pixel clock & IP clock.
  11   - resets: reset to be used by the device (defined by use of RCC macro).
  12   Required nodes:
  13     - Video port for RGB output.
  14
  15 * STMicroelectronics STM32 DSI controller specific extensions to Synopsys
  16   DesignWare MIPI DSI host controller
  17
  18 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
  19 DSI host controller. For all mandatory properties & nodes, please refer
  20 to the related documentation in [5].
  21
  22 Mandatory properties specific to STM32 DSI:
  23 - #address-cells: Should be <1>.
  24 - #size-cells: Should be <0>.
  25 - compatible: "st,stm32-dsi".
  26 - clock-names:
  27   - phy pll reference clock string name, must be "ref".
  28 - resets: see [5].
  29 - reset-names: see [5].
  30
  31 Mandatory nodes specific to STM32 DSI:
  32 - ports: A node containing DSI input & output port nodes with endpoint
  33   definitions as documented in [3] & [4].
  34   - port@0: DSI input port node, connected to the ltdc rgb output port.
  35   - port@1: DSI output port node, connected to a panel or a bridge input port.
  36 - panel or bridge node: A node containing the panel or bridge description as
  37   documented in [6].
  38   - port: panel or bridge port node, connected to the DSI output port (port@1).
  39
  40 Note: You can find more documentation in the following references
  41 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  42 [2] Documentation/devicetree/bindings/reset/reset.txt
  43 [3] Documentation/devicetree/bindings/media/video-interfaces.txt
  44 [4] Documentation/devicetree/bindings/graph.txt
  45 [5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
  46 [6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
  47
  48 Example 1: RGB panel
  49 / {
  50         ...
  51         soc {
  52         ...
  53                 ltdc: display-controller@40016800 {
  54                         compatible = "st,stm32-ltdc";
  55                         reg = <0x40016800 0x200>;
  56                         interrupts = <88>, <89>;
  57                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
  58                         clocks = <&rcc 1 CLK_LCD>;
  59                         clock-names = "lcd";
  60
  61                         port {
  62                                 ltdc_out_rgb: endpoint {
  63                                 };
  64                         };
  65                 };
  66         };
  67 };
  68
  69 Example 2: DSI panel
  70
  71 / {
  72         ...
  73         soc {
  74         ...
  75                 ltdc: display-controller@40016800 {
  76                         compatible = "st,stm32-ltdc";
  77                         reg = <0x40016800 0x200>;
  78                         interrupts = <88>, <89>;
  79                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
  80                         clocks = <&rcc 1 CLK_LCD>;
  81                         clock-names = "lcd";
  82
  83                         port {
  84                                 ltdc_out_dsi: endpoint {
  85                                         remote-endpoint = <&dsi_in>;
  86                                 };
  87                         };
  88                 };
  89
  90
  91                 dsi: dsi@40016c00 {
  92                         #address-cells = <1>;
  93                         #size-cells = <0>;
  94                         compatible = "st,stm32-dsi";
  95                         reg = <0x40016c00 0x800>;
  96                         clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
  97                         clock-names = "ref", "pclk";
  98                         resets = <&rcc STM32F4_APB2_RESET(DSI)>;
  99                         reset-names = "apb";
 100
 101                         ports {
 102                                 #address-cells = <1>;
 103                                 #size-cells = <0>;
 104
 105                                 port@0 {
 106                                         reg = <0>;
 107                                         dsi_in: endpoint {
 108                                                 remote-endpoint = <&ltdc_out_dsi>;
 109                                         };
 110                                 };
 111
 112                                 port@1 {
 113                                         reg = <1>;
 114                                         dsi_out: endpoint {
 115                                                 remote-endpoint = <&dsi_in_panel>;
 116                                         };
 117                                 };
 118
 119                         };
 120
 121                         panel-dsi@0 {
 122                                 reg = <0>; /* dsi virtual channel (0..3) */
 123                                 compatible = ...;
 124                                 enable-gpios = ...;
 125
 126                                 port {
 127                                         dsi_in_panel: endpoint {
 128                                                 remote-endpoint = <&dsi_out>;
 129                                         };
 130                                 };
 131
 132                         };
 133
 134                 };
 135
 136         };
 137 };