1 device-tree bindings for rockchip soc display controller (vop)
3 VOP (Visual Output Processor) is the Display Controller for the Rockchip
4 series of SoCs which transfers the image data from a video memory
5 buffer to an external LCD interface.
8 - compatible: value should be one of the following
10 "rockchip,rk3126-vop";
11 "rockchip,px30-vop-lit";
12 "rockchip,px30-vop-big";
13 "rockchip,rk3188-vop";
14 "rockchip,rk3288-vop";
15 "rockchip,rk3368-vop";
16 "rockchip,rk3366-vop";
17 "rockchip,rk3399-vop-big";
18 "rockchip,rk3399-vop-lit";
19 "rockchip,rk3228-vop";
20 "rockchip,rk3328-vop";
22 - interrupts: should contain a list of all VOP IP block interrupts in the
23 order: VSYNC, LCD_SYSTEM. The interrupt specifier
24 format depends on the interrupt controller used.
26 - clocks: must include clock specifiers corresponding to entries in the
29 - clock-names: Must contain
30 aclk_vop: for ddr buffer transfer.
31 hclk_vop: for ahb bus to R/W the phy regs.
32 dclk_vop: pixel clock.
34 - resets: Must contain an entry for each entry in reset-names.
35 See ../reset/reset.txt for details.
36 - reset-names: Must include the following entries:
41 - iommus: required a iommu node
43 - port: A port node with endpoint definitions as defined in
44 Documentation/devicetree/bindings/media/video-interfaces.txt.
47 SoC specific DT entry:
49 compatible = "rockchip,rk3288-vop";
50 reg = <0xff930000 0x19c>;
51 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
52 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
53 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
54 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
55 reset-names = "axi", "ahb", "dclk";
60 vopb_out_edp: endpoint@0 {
62 remote-endpoint=<&edp_in_vopb>;
64 vopb_out_hdmi: endpoint@1 {
66 remote-endpoint=<&hdmi_in_vopb>;