Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt

   1 Rockchip DWC HDMI TX Encoder
   2 ============================
   3
   4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
   5 with a companion PHY IP.
   6
   7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
   8 Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
   9 following device-specific properties.
  10
  11
  12 Required properties:
  13
  14 - compatible: should be one of the following:
  15                 "rockchip,rk3228-dw-hdmi"
  16                 "rockchip,rk3288-dw-hdmi"
  17                 "rockchip,rk3328-dw-hdmi"
  18                 "rockchip,rk3399-dw-hdmi"
  19 - reg: See dw_hdmi.txt.
  20 - reg-io-width: See dw_hdmi.txt. Shall be 4.
  21 - interrupts: HDMI interrupt number
  22 - clocks: See dw_hdmi.txt.
  23 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
  24 - ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
  25   corresponding to the video input of the controller. The port shall have two
  26   endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
  27 - rockchip,grf: Shall reference the GRF to mux vopl/vopb.
  28
  29 Optional properties
  30
  31 - ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
  32   or the functionally-reduced I2C master contained in the DWC HDMI. When
  33   connected to a system I2C master this property contains a phandle to that
  34   I2C master controller.
  35 - clock-names: See dw_hdmi.txt. The "cec" clock is optional.
  36 - clock-names: May contain "cec" as defined in dw_hdmi.txt.
  37 - clock-names: May contain "grf", power for grf io.
  38 - clock-names: May contain "vpll", external clock for some hdmi phy.
  39 - phys: from general PHY binding: the phandle for the PHY device.
  40 - phy-names: Should be "hdmi" if phys references an external phy.
  41
  42 Optional pinctrl entry:
  43 - If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
  44   will switch to the unwedge pinctrl state for 10ms if it ever gets an
  45   i2c timeout.  It's intended that this unwedge pinctrl entry will
  46   cause the SDA line to be driven low to work around a hardware
  47   errata.
  48
  49 Example:
  50
  51 hdmi: hdmi@ff980000 {
  52         compatible = "rockchip,rk3288-dw-hdmi";
  53         reg = <0xff980000 0x20000>;
  54         reg-io-width = <4>;
  55         ddc-i2c-bus = <&i2c5>;
  56         rockchip,grf = <&grf>;
  57         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  58         clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
  59         clock-names = "iahb", "isfr";
  60         ports {
  61                 hdmi_in: port {
  62                         #address-cells = <1>;
  63                         #size-cells = <0>;
  64                         hdmi_in_vopb: endpoint@0 {
  65                                 reg = <0>;
  66                                 remote-endpoint = <&vopb_out_hdmi>;
  67                         };
  68                         hdmi_in_vopl: endpoint@1 {
  69                                 reg = <1>;
  70                                 remote-endpoint = <&vopl_out_hdmi>;
  71                         };
  72                 };
  73         };
  74 };