Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt

   1 Rockchip DWC HDMI TX Encoder
   2 ============================
   3
   4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
   5 with a companion PHY IP.
   6
   7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
   8 Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
   9 following device-specific properties.
  10
  11
  12 Required properties:
  13
  14 - compatible: should be one of the following:
  15                 "rockchip,rk3288-dw-hdmi"
  16                 "rockchip,rk3328-dw-hdmi"
  17                 "rockchip,rk3399-dw-hdmi"
  18 - reg: See dw_hdmi.txt.
  19 - reg-io-width: See dw_hdmi.txt. Shall be 4.
  20 - interrupts: HDMI interrupt number
  21 - clocks: See dw_hdmi.txt.
  22 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
  23 - ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
  24   corresponding to the video input of the controller. The port shall have two
  25   endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
  26 - rockchip,grf: Shall reference the GRF to mux vopl/vopb.
  27
  28 Optional properties
  29
  30 - ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
  31   or the functionally-reduced I2C master contained in the DWC HDMI. When
  32   connected to a system I2C master this property contains a phandle to that
  33   I2C master controller.
  34 - clock-names: See dw_hdmi.txt. The "cec" clock is optional.
  35 - clock-names: May contain "cec" as defined in dw_hdmi.txt.
  36 - clock-names: May contain "grf", power for grf io.
  37 - clock-names: May contain "vpll", external clock for some hdmi phy.
  38 - phys: from general PHY binding: the phandle for the PHY device.
  39 - phy-names: Should be "hdmi" if phys references an external phy.
  40
  41 Example:
  42
  43 hdmi: hdmi@ff980000 {
  44         compatible = "rockchip,rk3288-dw-hdmi";
  45         reg = <0xff980000 0x20000>;
  46         reg-io-width = <4>;
  47         ddc-i2c-bus = <&i2c5>;
  48         rockchip,grf = <&grf>;
  49         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  50         clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
  51         clock-names = "iahb", "isfr";
  52         ports {
  53                 hdmi_in: port {
  54                         #address-cells = <1>;
  55                         #size-cells = <0>;
  56                         hdmi_in_vopb: endpoint@0 {
  57                                 reg = <0>;
  58                                 remote-endpoint = <&vopb_out_hdmi>;
  59                         };
  60                         hdmi_in_vopl: endpoint@1 {
  61                                 reg = <1>;
  62                                 remote-endpoint = <&vopl_out_hdmi>;
  63                         };
  64                 };
  65         };
  66 };