1 Rockchip DWC HDMI TX Encoder
2 ============================
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
5 with a companion PHY IP.
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
8 Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
9 following device-specific properties.
14 - compatible: Shall contain "rockchip,rk3288-dw-hdmi".
15 - reg: See dw_hdmi.txt.
16 - reg-io-width: See dw_hdmi.txt. Shall be 4.
17 - interrupts: HDMI interrupt number
18 - clocks: See dw_hdmi.txt.
19 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
20 - ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
21 corresponding to the video input of the controller. The port shall have two
22 endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
23 - rockchip,grf: Shall reference the GRF to mux vopl/vopb.
27 - ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
28 or the functionally-reduced I2C master contained in the DWC HDMI. When
29 connected to a system I2C master this property contains a phandle to that
30 I2C master controller.
31 - clock-names: See dw_hdmi.txt. The "cec" clock is optional.
32 - clock-names: May contain "cec" as defined in dw_hdmi.txt.
38 compatible = "rockchip,rk3288-dw-hdmi";
39 reg = <0xff980000 0x20000>;
41 ddc-i2c-bus = <&i2c5>;
42 rockchip,grf = <&grf>;
43 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
44 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
45 clock-names = "iahb", "isfr";
51 hdmi_in_vopb: endpoint@0 {
53 remote-endpoint = <&vopb_out_hdmi>;
55 hdmi_in_vopl: endpoint@1 {
57 remote-endpoint = <&vopl_out_hdmi>;