Documentation/devicetree/bindings/display/renesas,du.txt

   1 * Renesas R-Car Display Unit (DU)
   2
   3 Required Properties:
   4
   5   - compatible: must be one of the following.
   6     - "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
   7     - "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
   8     - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
   9     - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
  10     - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
  11     - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU
  12     - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
  13     - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
  14     - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
  15     - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
  16     - "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
  17     - "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
  18     - "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
  19
  20   - reg: the memory-mapped I/O registers base address and length
  21
  22   - interrupt-parent: phandle of the parent interrupt controller.
  23   - interrupts: Interrupt specifiers for the DU interrupts.
  24
  25   - clocks: A list of phandles + clock-specifier pairs, one for each entry in
  26     the clock-names property.
  27   - clock-names: Name of the clocks. This property is model-dependent.
  28     - R8A7779 uses a single functional clock. The clock doesn't need to be
  29       named.
  30     - All other DU instances use one functional clock per channel The
  31       functional clocks must be named "du.x" with "x" being the channel
  32       numerical index.
  33     - In addition to the functional clocks, all DU versions also support
  34       externally supplied pixel clocks. Those clocks are optional. When
  35       supplied they must be named "dclkin.x" with "x" being the input clock
  36       numerical index.
  37
  38   - vsps: A list of phandle and channel index tuples to the VSPs that handle
  39     the memory interfaces for the DU channels. The phandle identifies the VSP
  40     instance that serves the DU channel, and the channel index identifies the
  41     LIF instance in that VSP.
  42
  43 Required nodes:
  44
  45 The connections to the DU output video ports are modeled using the OF graph
  46 bindings specified in Documentation/devicetree/bindings/graph.txt.
  47
  48 The following table lists for each supported model the port number
  49 corresponding to each DU output.
  50
  51                         Port0          Port1          Port2          Port3
  52 -----------------------------------------------------------------------------
  53  R8A7743 (RZ/G1M)       DPAD 0         LVDS 0         -              -
  54  R8A7745 (RZ/G1E)       DPAD 0         DPAD 1         -              -
  55  R8A7779 (R-Car H1)     DPAD 0         DPAD 1         -              -
  56  R8A7790 (R-Car H2)     DPAD 0         LVDS 0         LVDS 1         -
  57  R8A7791 (R-Car M2-W)   DPAD 0         LVDS 0         -              -
  58  R8A7792 (R-Car V2H)    DPAD 0         DPAD 1         -              -
  59  R8A7793 (R-Car M2-N)   DPAD 0         LVDS 0         -              -
  60  R8A7794 (R-Car E2)     DPAD 0         DPAD 1         -              -
  61  R8A7795 (R-Car H3)     DPAD 0         HDMI 0         HDMI 1         LVDS 0
  62  R8A7796 (R-Car M3-W)   DPAD 0         HDMI 0         LVDS 0         -
  63  R8A77965 (R-Car M3-N)  DPAD 0         HDMI 0         LVDS 0         -
  64  R8A77970 (R-Car V3M)   DPAD 0         LVDS 0         -              -
  65  R8A77995 (R-Car D3)    DPAD 0         LVDS 0         LVDS 1         -
  66
  67
  68 Example: R8A7795 (R-Car H3) ES2.0 DU
  69
  70         du: display@feb00000 {
  71                 compatible = "renesas,du-r8a7795";
  72                 reg = <0 0xfeb00000 0 0x80000>;
  73                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
  77                 clocks = <&cpg CPG_MOD 724>,
  78                          <&cpg CPG_MOD 723>,
  79                          <&cpg CPG_MOD 722>,
  80                          <&cpg CPG_MOD 721>;
  81                 clock-names = "du.0", "du.1", "du.2", "du.3";
  82                 vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
  83
  84                 ports {
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87
  88                         port@0 {
  89                                 reg = <0>;
  90                                 du_out_rgb: endpoint {
  91                                 };
  92                         };
  93                         port@1 {
  94                                 reg = <1>;
  95                                 du_out_hdmi0: endpoint {
  96                                         remote-endpoint = <&dw_hdmi0_in>;
  97                                 };
  98                         };
  99                         port@2 {
 100                                 reg = <2>;
 101                                 du_out_hdmi1: endpoint {
 102                                         remote-endpoint = <&dw_hdmi1_in>;
 103                                 };
 104                         };
 105                         port@3 {
 106                                 reg = <3>;
 107                                 du_out_lvds0: endpoint {
 108                                 };
 109                         };
 110                 };
 111         };