Documentation/devicetree/bindings/display/msm/gmu.txt

   1 Qualcomm adreno/snapdragon GMU (Graphics management unit)
   2
   3 The GMU is a programmable power controller for the GPU. the CPU controls the
   4 GMU which in turn handles power controls for the GPU.
   5
   6 Required properties:
   7 - compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
   8     for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
   9   Note that you need to list the less specific "qcom,adreno-gmu"
  10   for generic matches and the more specific identifier to identify
  11   the specific device.
  12 - reg: Physical base address and length of the GMU registers.
  13 - reg-names: Matching names for the register regions
  14   * "gmu"
  15   * "gmu_pdc"
  16   * "gmu_pdc_seg"
  17 - interrupts: The interrupt signals from the GMU.
  18 - interrupt-names: Matching names for the interrupts
  19   * "hfi"
  20   * "gmu"
  21 - clocks: phandles to the device clocks
  22 - clock-names: Matching names for the clocks
  23    * "gmu"
  24    * "cxo"
  25    * "axi"
  26    * "mnoc"
  27 - power-domains: should be:
  28         <&clock_gpucc GPU_CX_GDSC>
  29         <&clock_gpucc GPU_GX_GDSC>
  30 - power-domain-names: Matching names for the power domains
  31 - iommus: phandle to the adreno iommu
  32 - operating-points-v2: phandle to the OPP operating points
  33
  34 Optional properties:
  35 - sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
  36         SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
  37
  38 Example:
  39
  40 / {
  41         ...
  42
  43         gmu: gmu@506a000 {
  44                 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
  45
  46                 reg = <0x506a000 0x30000>,
  47                         <0xb280000 0x10000>,
  48                         <0xb480000 0x10000>;
  49                 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
  50
  51                 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  52                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
  53                 interrupt-names = "hfi", "gmu";
  54
  55                 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
  56                         <&gpucc GPU_CC_CXO_CLK>,
  57                         <&gcc GCC_DDRSS_GPU_AXI_CLK>,
  58                         <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
  59                 clock-names = "gmu", "cxo", "axi", "memnoc";
  60
  61                 power-domains = <&gpucc GPU_CX_GDSC>,
  62                                 <&gpucc GPU_GX_GDSC>;
  63                 power-domain-names = "cx", "gx";
  64
  65                 iommus = <&adreno_smmu 5>;
  66
  67                 operating-points-v2 = <&gmu_opp_table>;
  68         };
  69 };
  70
  71 a3xx example with OCMEM support:
  72
  73 / {
  74         ...
  75
  76         gpu: adreno@fdb00000 {
  77                 compatible = "qcom,adreno-330.2",
  78                              "qcom,adreno";
  79                 reg = <0xfdb00000 0x10000>;
  80                 reg-names = "kgsl_3d0_reg_memory";
  81                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-names = "kgsl_3d0_irq";
  83                 clock-names = "core",
  84                               "iface",
  85                               "mem_iface";
  86                 clocks = <&mmcc OXILI_GFX3D_CLK>,
  87                          <&mmcc OXILICX_AHB_CLK>,
  88                          <&mmcc OXILICX_AXI_CLK>;
  89                 sram = <&gmu_sram>;
  90                 power-domains = <&mmcc OXILICX_GDSC>;
  91                 operating-points-v2 = <&gpu_opp_table>;
  92                 iommus = <&gpu_iommu 0>;
  93         };
  94
  95         ocmem@fdd00000 {
  96                 compatible = "qcom,msm8974-ocmem";
  97
  98                 reg = <0xfdd00000 0x2000>,
  99                       <0xfec00000 0x180000>;
 100                 reg-names = "ctrl",
 101                              "mem";
 102
 103                 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
 104                          <&mmcc OCMEMCX_OCMEMNOC_CLK>;
 105                 clock-names = "core",
 106                               "iface";
 107
 108                 #address-cells = <1>;
 109                 #size-cells = <1>;
 110
 111                 gmu_sram: gmu-sram@0 {
 112                         reg = <0x0 0x100000>;
 113                         ranges = <0 0 0xfec00000 0x100000>;
 114                 };
 115         };
 116 };