1 Qualcomm adreno/snapdragon GMU (Graphics management unit)
3 The GMU is a programmable power controller for the GPU. the CPU controls the
4 GMU which in turn handles power controls for the GPU.
7 - compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
8 for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
9 Note that you need to list the less specific "qcom,adreno-gmu"
10 for generic matches and the more specific identifier to identify
12 - reg: Physical base address and length of the GMU registers.
13 - reg-names: Matching names for the register regions
17 - interrupts: The interrupt signals from the GMU.
18 - interrupt-names: Matching names for the interrupts
21 - clocks: phandles to the device clocks
22 - clock-names: Matching names for the clocks
27 - power-domains: should be <&clock_gpucc GPU_CX_GDSC>
28 - iommus: phandle to the adreno iommu
29 - operating-points-v2: phandle to the OPP operating points
37 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
39 reg = <0x506a000 0x30000>,
42 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
44 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
46 interrupt-names = "hfi", "gmu";
48 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
49 <&gpucc GPU_CC_CXO_CLK>,
50 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
51 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
52 clock-names = "gmu", "cxo", "axi", "memnoc";
54 power-domains = <&gpucc GPU_CX_GDSC>;
55 iommus = <&adreno_smmu 5>;
57 operating-points-v2 = <&gmu_opp_table>;