Documentation/devicetree/bindings/display/msm/gmu.txt

   1 Qualcomm adreno/snapdragon GMU (Graphics management unit)
   2
   3 The GMU is a programmable power controller for the GPU. the CPU controls the
   4 GMU which in turn handles power controls for the GPU.
   5
   6 Required properties:
   7 - compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
   8     for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
   9   Note that you need to list the less specific "qcom,adreno-gmu"
  10   for generic matches and the more specific identifier to identify
  11   the specific device.
  12 - reg: Physical base address and length of the GMU registers.
  13 - reg-names: Matching names for the register regions
  14   * "gmu"
  15   * "gmu_pdc"
  16   * "gmu_pdc_seg"
  17 - interrupts: The interrupt signals from the GMU.
  18 - interrupt-names: Matching names for the interrupts
  19   * "hfi"
  20   * "gmu"
  21 - clocks: phandles to the device clocks
  22 - clock-names: Matching names for the clocks
  23    * "gmu"
  24    * "cxo"
  25    * "axi"
  26    * "mnoc"
  27 - power-domains: should be <&clock_gpucc GPU_CX_GDSC>
  28 - iommus: phandle to the adreno iommu
  29 - operating-points-v2: phandle to the OPP operating points
  30
  31 Example:
  32
  33 / {
  34         ...
  35
  36         gmu: gmu@506a000 {
  37                 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
  38
  39                 reg = <0x506a000 0x30000>,
  40                         <0xb280000 0x10000>,
  41                         <0xb480000 0x10000>;
  42                 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
  43
  44                 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  45                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
  46                 interrupt-names = "hfi", "gmu";
  47
  48                 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
  49                         <&gpucc GPU_CC_CXO_CLK>,
  50                         <&gcc GCC_DDRSS_GPU_AXI_CLK>,
  51                         <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
  52                 clock-names = "gmu", "cxo", "axi", "memnoc";
  53
  54                 power-domains = <&gpucc GPU_CX_GDSC>;
  55                 iommus = <&adreno_smmu 5>;
  56
  57                 operating-points-v2 = <&gmu_opp_table>;
  58         };
  59 };