1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
21 For DSIv2, we need an additional clock:
23 For DSI6G v2.0 onwards, we need also need the clock:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
27 by a DSI PHY block. See [1] for details on clock bindings.
28 - vdd-supply: phandle to vdd regulator device node
29 - vddio-supply: phandle to vdd-io regulator device node
30 - vdda-supply: phandle to vdda regulator device node
31 - phys: phandle to DSI PHY device node
32 - phy-names: the name of the corresponding PHY device
33 - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34 - ports: Contains 2 DSI controller ports as child nodes. Each port contains
35 an endpoint subnode as defined in [2] and [3].
38 - panel@0: Node of panel connected to this DSI controller.
39 See files in [4] for each supported panel.
40 - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
41 driving a panel which needs 2 DSI links.
42 - qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43 the master link of the 2-DSI panel.
44 - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45 driving a 2-DSI panel whose 2 links need receive command simultaneously.
46 - interrupt-parent: phandle to the MDP block if the interrupt signal is routed
48 - pinctrl-names: the pin control state names; should contain "default"
49 - pinctrl-0: the default pinctrl state (active)
50 - pinctrl-n: the "sleep" pinctrl state
51 - ports: contains DSI controller input and output ports as children, each
52 containing one endpoint subnode.
54 DSI Endpoint properties:
55 - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
56 input endpoint. For port@1, set to the MDP interface output. See [2] for
59 - data-lanes: this describes how the physical DSI data lanes are mapped
60 to the logical lanes on the given platform. The value contained in
61 index n describes what physical lane is mapped to the logical lane n
62 (DATAn, where n lies between 0 and 3). The clock lane position is fixed
63 and can't be changed. Hence, they aren't a part of the DT bindings. See
64 [3] for more info on the data-lanes property.
68 data-lanes = <3 0 1 2>;
70 The above mapping describes that the logical data lane DATA0 is mapped to
71 the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
72 to phys DATA1 and logic DATA3 to phys DATA2.
74 There are only a limited number of physical to logical mappings possible:
86 - compatible: Could be the following
87 * "qcom,dsi-phy-28nm-hpm"
88 * "qcom,dsi-phy-28nm-lp"
90 * "qcom,dsi-phy-28nm-8960"
93 - reg: Physical base address and length of the registers of PLL, PHY. Some
94 revisions require the PHY regulator base address, whereas others require the
95 PHY lane base address. See below for each PHY revision.
96 - reg-names: The names of register regions. The following regions are required:
97 For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
100 * "dsi_phy_regulator"
101 For DSI 14nm and 10nm PHYs:
105 - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
106 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
107 - power-domains: Should be <&mmcc MDSS_GDSC>.
108 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
109 - clock-names: the following clocks are required:
111 For 28nm HPM/LP, 28nm 8960 PHYs:
112 - vddio-supply: phandle to vdd-io regulator device node
114 - vddio-supply: phandle to vdd-io regulator device node
115 - vcca-supply: phandle to vcca regulator device node
117 - vcca-supply: phandle to vcca regulator device node
119 - vdds-supply: phandle to vdds regulator device node
122 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
125 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
126 [2] Documentation/devicetree/bindings/graph.txt
127 [3] Documentation/devicetree/bindings/media/video-interfaces.txt
128 [4] Documentation/devicetree/bindings/display/panel/
132 compatible = "qcom,mdss-dsi-ctrl";
133 qcom,dsi-host-index = <0>;
134 interrupt-parent = <&mdp>;
136 reg-names = "dsi_ctrl";
137 reg = <0xfd922800 0x200>;
138 power-domains = <&mmcc MDSS_GDSC>;
148 <&mmcc MDSS_AXI_CLK>,
149 <&mmcc MDSS_BYTE0_CLK>,
150 <&mmcc MDSS_ESC0_CLK>,
151 <&mmcc MMSS_MISC_AHB_CLK>,
152 <&mmcc MDSS_AHB_CLK>,
153 <&mmcc MDSS_MDP_CLK>,
154 <&mmcc MDSS_PCLK0_CLK>;
157 <&mmcc BYTE0_CLK_SRC>,
158 <&mmcc PCLK0_CLK_SRC>;
159 assigned-clock-parents =
163 vdda-supply = <&pma8084_l2>;
164 vdd-supply = <&pma8084_l22>;
165 vddio-supply = <&pma8084_l12>;
168 phy-names ="dsi-phy";
174 pinctrl-names = "default", "sleep";
175 pinctrl-0 = <&dsi_active>;
176 pinctrl-1 = <&dsi_suspend>;
179 #address-cells = <1>;
185 remote-endpoint = <&mdp_intf1_out>;
192 remote-endpoint = <&panel_in>;
193 data-lanes = <0 1 2 3>;
199 compatible = "sharp,lq101r1sx01";
201 link2 = <&secondary>;
203 power-supply = <...>;
208 remote-endpoint = <&dsi0_out>;
214 dsi_phy0: dsi-phy@fd922a00 {
215 compatible = "qcom,dsi-phy-28nm-hpm";
216 qcom,dsi-phy-index = <0>;
221 reg = <0xfd922a00 0xd4>,
224 clock-names = "iface";
225 clocks = <&mmcc MDSS_AHB_CLK>;
227 vddio-supply = <&pma8084_l12>;
229 qcom,dsi-phy-regulator-ldo-mode;