Documentation/devicetree/bindings/display/arm,komeda.txt

   1 Device Tree bindings for Arm Komeda display driver
   2
   3 Required properties:
   4 - compatible: Should be "arm,mali-d71"
   5 - reg: Physical base address and length of the registers in the system
   6 - interrupts: the interrupt line number of the device in the system
   7 - clocks: A list of phandle + clock-specifier pairs, one for each entry
   8     in 'clock-names'
   9 - clock-names: A list of clock names. It should contain:
  10       - "mclk": for the main processor clock
  11       - "pclk": for the APB interface clock
  12 - #address-cells: Must be 1
  13 - #size-cells: Must be 0
  14
  15 Required properties for sub-node: pipeline@nq
  16 Each device contains one or two pipeline sub-nodes (at least one), each
  17 pipeline node should provide properties:
  18 - reg: Zero-indexed identifier for the pipeline
  19 - clocks: A list of phandle + clock-specifier pairs, one for each entry
  20     in 'clock-names'
  21 - clock-names: should contain:
  22       - "pxclk": pixel clock
  23       - "aclk": AXI interface clock
  24
  25 - port: each pipeline connect to an encoder input port. The connection is
  26     modeled using the OF graph bindings specified in
  27     Documentation/devicetree/bindings/graph.txt
  28
  29 Optional properties:
  30   - memory-region: phandle to a node describing memory (see
  31     Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
  32     to be used for the framebuffer; if not present, the framebuffer may
  33     be located anywhere in memory.
  34
  35 Example:
  36 / {
  37         ...
  38
  39         dp0: display@c00000 {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42                 compatible = "arm,mali-d71";
  43                 reg = <0xc00000 0x20000>;
  44                 interrupts = <0 168 4>;
  45                 clocks = <&dpu_mclk>, <&dpu_aclk>;
  46                 clock-names = "mclk", "pclk";
  47
  48                 dp0_pipe0: pipeline@0 {
  49                         clocks = <&fpgaosc2>, <&dpu_aclk>;
  50                         clock-names = "pxclk", "aclk";
  51                         reg = <0>;
  52
  53                         port {
  54                                 dp0_pipe0_out: endpoint {
  55                                         remote-endpoint = <&db_dvi0_in>;
  56                                 };
  57                         };
  58                 };
  59
  60                 dp0_pipe1: pipeline@1 {
  61                         clocks = <&fpgaosc2>, <&dpu_aclk>;
  62                         clock-names = "pxclk", "aclk";
  63                         reg = <1>;
  64
  65                         port {
  66                                 dp0_pipe1_out: endpoint {
  67                                         remote-endpoint = <&db_dvi1_in>;
  68                                 };
  69                         };
  70                 };
  71         };
  72         ...
  73 };