1 Amlogic Meson Display Controller
2 ================================
4 The Amlogic Meson Display controller is composed of several components
5 that are going to be documented below:
7 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
8 | vd1 _______ _____________ _________________ | |
9 D |-------| |----| | | | | HDMI PLL |
10 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
11 R |-------| |----| Processing | | | | |
12 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
13 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
14 A | osd1 | | | Blenders | | Encl ----------|----|---------------|
15 M |-------|______|----|____________| |________________| | |
16 ___|__________________________________________________________|_______________|
22 The Video Input Unit is in charge of the pixel scanout from the DDR memory.
23 It fetches the frames addresses, stride and parameters from the "Canvas" memory.
24 This part is also in charge of the CSC (Colorspace Conversion).
25 It can handle 2 OSD Planes and 2 Video Planes.
27 VPP: Video Post Processing
28 --------------------------
30 The Video Post Processing is in charge of the scaling and blending of the
31 various planes into a single pixel stream.
32 There is a special "pre-blending" used by the video planes with a dedicated
33 scaler and a "post-blending" to merge with the OSD Planes.
34 The OSD planes also have a dedicated scaler for one of the OSD.
39 The VENC is composed of the multiple pixel encoders :
40 - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
41 - ENCP : Progressive Video Encoder for HDMI
42 - ENCL : LCD LVDS Encoder
43 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
44 tree and provides the scanout clock to the VPP and VIU.
45 The ENCI is connected to a single VDAC for Composite Output.
46 The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
51 VPU: Video Processing Unit
52 --------------------------
55 - compatible: value should be different for each SoC family as :
56 - GXBB (S905) : "amlogic,meson-gxbb-vpu"
57 - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
58 - GXM (S912) : "amlogic,meson-gxm-vpu"
59 followed by the common "amlogic,meson-gx-vpu"
60 - G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-vpu"
61 - reg: base address and size of he following memory-mapped regions :
64 - reg-names: should contain the names of the previous memory regions
65 - interrupts: should contain the VENC Vsync interrupt number
66 - amlogic,canvas: phandle to canvas provider node as described in the file
67 ../soc/amlogic/amlogic,canvas.txt
70 - power-domains: Optional phandle to associated power domain as described in
71 the file ../power/power_domain.txt
75 The connections to the VPU output video ports are modeled using the OF graph
76 bindings specified in Documentation/devicetree/bindings/graph.txt.
78 The following table lists for each supported model the port number
79 corresponding to each VPU output.
82 -----------------------------------------
83 S905 (GXBB) CVBS VDAC HDMI-TX
84 S905X (GXL) CVBS VDAC HDMI-TX
85 S905D (GXL) CVBS VDAC HDMI-TX
86 S912 (GXM) CVBS VDAC HDMI-TX
87 S905X2 (G12A) CVBS VDAC HDMI-TX
88 S905Y2 (G12A) CVBS VDAC HDMI-TX
89 S905D2 (G12A) CVBS VDAC HDMI-TX
94 compatible = "composite-video-connector";
97 tv_connector_in: endpoint {
98 remote-endpoint = <&cvbs_vdac_out>;
104 compatible = "amlogic,meson-gxbb-vpu";
105 reg = <0x0 0xd0100000 0x0 0x100000>,
106 <0x0 0xc883c000 0x0 0x1000>,
107 <0x0 0xc8838000 0x0 0x1000>;
108 reg-names = "vpu", "hhi", "dmc";
109 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
110 #address-cells = <1>;
113 /* CVBS VDAC output port */
117 cvbs_vdac_out: endpoint {
118 remote-endpoint = <&tv_connector_in>;