Documentation/devicetree/bindings/devfreq/exynos-bus.txt

   1 * Generic Exynos Bus frequency device
   2
   3 The Samsung Exynos SoC has many buses for data transfer between DRAM
   4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
   5 for buses. Generally, each bus of Exynos SoC includes a source clock
   6 and a power line, which are able to change the clock frequency
   7 of the bus in runtime. To monitor the usage of each bus in runtime,
   8 the driver uses the PPMU (Platform Performance Monitoring Unit), which
   9 is able to measure the current load of sub-blocks.
  10
  11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
  12 The each AXI bus has the owned source clock but, has not the only owned
  13 power line. The power line might be shared among one more sub-blocks.
  14 So, we can divide into two type of device as the role of each sub-block.
  15 There are two type of bus devices as following:
  16 - parent bus device
  17 - passive bus device
  18
  19 Basically, parent and passive bus device share the same power line.
  20 The parent bus device can only change the voltage of shared power line
  21 and the rest bus devices (passive bus device) depend on the decision of
  22 the parent bus device. If there are three blocks which share the VDD_xxx
  23 power line, Only one block should be parent device and then the rest blocks
  24 should depend on the parent device as passive device.
  25
  26         VDD_xxx |--- A block (parent)
  27                 |--- B block (passive)
  28                 |--- C block (passive)
  29
  30 There are a little different composition among Exynos SoC because each Exynos
  31 SoC has different sub-blocks. Therefore, such difference should be specified
  32 in devicetree file instead of each device driver. In result, this driver
  33 is able to support the bus frequency for all Exynos SoCs.
  34
  35 Required properties for all bus devices:
  36 - compatible: Should be "samsung,exynos-bus".
  37 - clock-names : the name of clock used by the bus, "bus".
  38 - clocks : phandles for clock specified in "clock-names" property.
  39 - operating-points-v2: the OPP table including frequency/voltage information
  40   to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
  41
  42 Required properties only for parent bus device:
  43 - vdd-supply: the regulator to provide the buses with the voltage.
  44 - devfreq-events: the devfreq-event device to monitor the current utilization
  45   of buses.
  46
  47 Required properties only for passive bus device:
  48 - devfreq: the parent bus device.
  49
  50 Optional properties only for parent bus device:
  51 - exynos,saturation-ratio: the percentage value which is used to calibrate
  52                         the performance count against total cycle count.
  53 - exynos,voltage-tolerance: the percentage value for bus voltage tolerance
  54                         which is used to calculate the max voltage.
  55
  56 Detailed correlation between sub-blocks and power line according to Exynos SoC:
  57 - In case of Exynos3250, there are two power line as following:
  58         VDD_MIF |--- DMC
  59
  60         VDD_INT |--- LEFTBUS (parent device)
  61                 |--- PERIL
  62                 |--- MFC
  63                 |--- G3D
  64                 |--- RIGHTBUS
  65                 |--- PERIR
  66                 |--- FSYS
  67                 |--- LCD0
  68                 |--- PERIR
  69                 |--- ISP
  70                 |--- CAM
  71
  72 - In case of Exynos4210, there is one power line as following:
  73         VDD_INT |--- DMC (parent device)
  74                 |--- LEFTBUS
  75                 |--- PERIL
  76                 |--- MFC(L)
  77                 |--- G3D
  78                 |--- TV
  79                 |--- LCD0
  80                 |--- RIGHTBUS
  81                 |--- PERIR
  82                 |--- MFC(R)
  83                 |--- CAM
  84                 |--- FSYS
  85                 |--- GPS
  86                 |--- LCD0
  87                 |--- LCD1
  88
  89 - In case of Exynos4x12, there are two power line as following:
  90         VDD_MIF |--- DMC
  91
  92         VDD_INT |--- LEFTBUS (parent device)
  93                 |--- PERIL
  94                 |--- MFC(L)
  95                 |--- G3D
  96                 |--- TV
  97                 |--- IMAGE
  98                 |--- RIGHTBUS
  99                 |--- PERIR
 100                 |--- MFC(R)
 101                 |--- CAM
 102                 |--- FSYS
 103                 |--- GPS
 104                 |--- LCD0
 105                 |--- ISP
 106
 107 - In case of Exynos5422, there are two power line as following:
 108         VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
 109                 |--- DREX 1
 110
 111         VDD_INT |--- NoC_Core (parent device)
 112                 |--- G2D
 113                 |--- G3D
 114                 |--- DISP1
 115                 |--- NoC_WCORE
 116                 |--- GSCL
 117                 |--- MSCL
 118                 |--- ISP
 119                 |--- MFC
 120                 |--- GEN
 121                 |--- PERIS
 122                 |--- PERIC
 123                 |--- FSYS
 124                 |--- FSYS2
 125
 126 - In case of Exynos5433, there is VDD_INT power line as following:
 127         VDD_INT |--- G2D (parent device)
 128                 |--- MSCL
 129                 |--- GSCL
 130                 |--- JPEG
 131                 |--- MFC
 132                 |--- HEVC
 133                 |--- BUS0
 134                 |--- BUS1
 135                 |--- BUS2
 136                 |--- PERIS (Fixed clock rate)
 137                 |--- PERIC (Fixed clock rate)
 138                 |--- FSYS  (Fixed clock rate)
 139
 140 Example1:
 141         Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
 142         power line (regulator). The MIF (Memory Interface) AXI bus is used to
 143         transfer data between DRAM and CPU and uses the VDD_MIF regulator.
 144
 145         - MIF (Memory Interface) block
 146         : VDD_MIF |--- DMC (Dynamic Memory Controller)
 147
 148         - INT (Internal) block
 149         : VDD_INT |--- LEFTBUS (parent device)
 150                   |--- PERIL
 151                   |--- MFC
 152                   |--- G3D
 153                   |--- RIGHTBUS
 154                   |--- FSYS
 155                   |--- LCD0
 156                   |--- PERIR
 157                   |--- ISP
 158                   |--- CAM
 159
 160         - MIF bus's frequency/voltage table
 161         -----------------------
 162         |Lv| Freq   | Voltage |
 163         -----------------------
 164         |L1| 50000  |800000   |
 165         |L2| 100000 |800000   |
 166         |L3| 134000 |800000   |
 167         |L4| 200000 |825000   |
 168         |L5| 400000 |875000   |
 169         -----------------------
 170
 171         - INT bus's frequency/voltage table
 172         ----------------------------------------------------------
 173         |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
 174         | name|       |LCD0    |       |       |       ||        |
 175         |     |       |FSYS    |       |       |       ||        |
 176         |     |       |MFC     |       |       |       ||        |
 177         ----------------------------------------------------------
 178         |Mode |*parent|passive |passive|passive|passive||        |
 179         ----------------------------------------------------------
 180         |Lv   |Frequency                               ||Voltage |
 181         ----------------------------------------------------------
 182         |L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
 183         |L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
 184         |L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
 185         |L4   |134000 |134000  |200000 |200000 |       ||1000000 |
 186         |L5   |200000 |200000  |400000 |300000 |       ||1000000 |
 187         ----------------------------------------------------------
 188
 189 Example2 :
 190         The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
 191         is listed below:
 192
 193         bus_dmc: bus_dmc {
 194                 compatible = "samsung,exynos-bus";
 195                 clocks = <&cmu_dmc CLK_DIV_DMC>;
 196                 clock-names = "bus";
 197                 operating-points-v2 = <&bus_dmc_opp_table>;
 198                 status = "disabled";
 199         };
 200
 201         bus_dmc_opp_table: opp_table1 {
 202                 compatible = "operating-points-v2";
 203                 opp-shared;
 204
 205                 opp@50000000 {
 206                         opp-hz = /bits/ 64 <50000000>;
 207                         opp-microvolt = <800000>;
 208                 };
 209                 opp@100000000 {
 210                         opp-hz = /bits/ 64 <100000000>;
 211                         opp-microvolt = <800000>;
 212                 };
 213                 opp@134000000 {
 214                         opp-hz = /bits/ 64 <134000000>;
 215                         opp-microvolt = <800000>;
 216                 };
 217                 opp@200000000 {
 218                         opp-hz = /bits/ 64 <200000000>;
 219                         opp-microvolt = <825000>;
 220                 };
 221                 opp@400000000 {
 222                         opp-hz = /bits/ 64 <400000000>;
 223                         opp-microvolt = <875000>;
 224                 };
 225         };
 226
 227         bus_leftbus: bus_leftbus {
 228                 compatible = "samsung,exynos-bus";
 229                 clocks = <&cmu CLK_DIV_GDL>;
 230                 clock-names = "bus";
 231                 operating-points-v2 = <&bus_leftbus_opp_table>;
 232                 status = "disabled";
 233         };
 234
 235         bus_rightbus: bus_rightbus {
 236                 compatible = "samsung,exynos-bus";
 237                 clocks = <&cmu CLK_DIV_GDR>;
 238                 clock-names = "bus";
 239                 operating-points-v2 = <&bus_leftbus_opp_table>;
 240                 status = "disabled";
 241         };
 242
 243         bus_lcd0: bus_lcd0 {
 244                 compatible = "samsung,exynos-bus";
 245                 clocks = <&cmu CLK_DIV_ACLK_160>;
 246                 clock-names = "bus";
 247                 operating-points-v2 = <&bus_leftbus_opp_table>;
 248                 status = "disabled";
 249         };
 250
 251         bus_fsys: bus_fsys {
 252                 compatible = "samsung,exynos-bus";
 253                 clocks = <&cmu CLK_DIV_ACLK_200>;
 254                 clock-names = "bus";
 255                 operating-points-v2 = <&bus_leftbus_opp_table>;
 256                 status = "disabled";
 257         };
 258
 259         bus_mcuisp: bus_mcuisp {
 260                 compatible = "samsung,exynos-bus";
 261                 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 262                 clock-names = "bus";
 263                 operating-points-v2 = <&bus_mcuisp_opp_table>;
 264                 status = "disabled";
 265         };
 266
 267         bus_isp: bus_isp {
 268                 compatible = "samsung,exynos-bus";
 269                 clocks = <&cmu CLK_DIV_ACLK_266>;
 270                 clock-names = "bus";
 271                 operating-points-v2 = <&bus_isp_opp_table>;
 272                 status = "disabled";
 273         };
 274
 275         bus_peril: bus_peril {
 276                 compatible = "samsung,exynos-bus";
 277                 clocks = <&cmu CLK_DIV_ACLK_100>;
 278                 clock-names = "bus";
 279                 operating-points-v2 = <&bus_peril_opp_table>;
 280                 status = "disabled";
 281         };
 282
 283         bus_mfc: bus_mfc {
 284                 compatible = "samsung,exynos-bus";
 285                 clocks = <&cmu CLK_SCLK_MFC>;
 286                 clock-names = "bus";
 287                 operating-points-v2 = <&bus_leftbus_opp_table>;
 288                 status = "disabled";
 289         };
 290
 291         bus_leftbus_opp_table: opp_table1 {
 292                 compatible = "operating-points-v2";
 293                 opp-shared;
 294
 295                 opp@50000000 {
 296                         opp-hz = /bits/ 64 <50000000>;
 297                         opp-microvolt = <900000>;
 298                 };
 299                 opp@80000000 {
 300                         opp-hz = /bits/ 64 <80000000>;
 301                         opp-microvolt = <900000>;
 302                 };
 303                 opp@100000000 {
 304                         opp-hz = /bits/ 64 <100000000>;
 305                         opp-microvolt = <1000000>;
 306                 };
 307                 opp@134000000 {
 308                         opp-hz = /bits/ 64 <134000000>;
 309                         opp-microvolt = <1000000>;
 310                 };
 311                 opp@200000000 {
 312                         opp-hz = /bits/ 64 <200000000>;
 313                         opp-microvolt = <1000000>;
 314                 };
 315         };
 316
 317         bus_mcuisp_opp_table: opp_table2 {
 318                 compatible = "operating-points-v2";
 319                 opp-shared;
 320
 321                 opp@50000000 {
 322                         opp-hz = /bits/ 64 <50000000>;
 323                 };
 324                 opp@80000000 {
 325                         opp-hz = /bits/ 64 <80000000>;
 326                 };
 327                 opp@100000000 {
 328                         opp-hz = /bits/ 64 <100000000>;
 329                 };
 330                 opp@200000000 {
 331                         opp-hz = /bits/ 64 <200000000>;
 332                 };
 333                 opp@400000000 {
 334                         opp-hz = /bits/ 64 <400000000>;
 335                 };
 336         };
 337
 338         bus_isp_opp_table: opp_table3 {
 339                 compatible = "operating-points-v2";
 340                 opp-shared;
 341
 342                 opp@50000000 {
 343                         opp-hz = /bits/ 64 <50000000>;
 344                 };
 345                 opp@80000000 {
 346                         opp-hz = /bits/ 64 <80000000>;
 347                 };
 348                 opp@100000000 {
 349                         opp-hz = /bits/ 64 <100000000>;
 350                 };
 351                 opp@200000000 {
 352                         opp-hz = /bits/ 64 <200000000>;
 353                 };
 354                 opp@300000000 {
 355                         opp-hz = /bits/ 64 <300000000>;
 356                 };
 357         };
 358
 359         bus_peril_opp_table: opp_table4 {
 360                 compatible = "operating-points-v2";
 361                 opp-shared;
 362
 363                 opp@50000000 {
 364                         opp-hz = /bits/ 64 <50000000>;
 365                 };
 366                 opp@80000000 {
 367                         opp-hz = /bits/ 64 <80000000>;
 368                 };
 369                 opp@100000000 {
 370                         opp-hz = /bits/ 64 <100000000>;
 371                 };
 372         };
 373
 374
 375         Usage case to handle the frequency and voltage of bus on runtime
 376         in exynos3250-rinato.dts is listed below:
 377
 378         &bus_dmc {
 379                 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
 380                 vdd-supply = <&buck1_reg>;      /* VDD_MIF */
 381                 status = "okay";
 382         };
 383
 384         &bus_leftbus {
 385                 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
 386                 vdd-supply = <&buck3_reg>;
 387                 status = "okay";
 388         };
 389
 390         &bus_rightbus {
 391                 devfreq = <&bus_leftbus>;
 392                 status = "okay";
 393         };
 394
 395         &bus_lcd0 {
 396                 devfreq = <&bus_leftbus>;
 397                 status = "okay";
 398         };
 399
 400         &bus_fsys {
 401                 devfreq = <&bus_leftbus>;
 402                 status = "okay";
 403         };
 404
 405         &bus_mcuisp {
 406                 devfreq = <&bus_leftbus>;
 407                 status = "okay";
 408         };
 409
 410         &bus_isp {
 411                 devfreq = <&bus_leftbus>;
 412                 status = "okay";
 413         };
 414
 415         &bus_peril {
 416                 devfreq = <&bus_leftbus>;
 417                 status = "okay";
 418         };
 419
 420         &bus_mfc {
 421                 devfreq = <&bus_leftbus>;
 422                 status = "okay";
 423         };