1 MediaTek cryptographic accelerators
4 - compatible: Should be "mediatek,eip97-crypto"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain the five crypto engines interrupts in numeric
7 order. These are global system and four descriptor rings.
8 - clocks: the clock used by the core
9 - clock-names: the names of the clock listed in the clocks property. These are
11 - power-domains: Must contain a reference to the PM domain.
15 crypto: crypto@1b240000 {
16 compatible = "mediatek,eip97-crypto";
17 reg = <0 0x1b240000 0 0x20000>;
18 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
19 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
20 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
21 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
22 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
23 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
24 <ðsys CLK_ETHSYS_CRYPTO>;
25 clock-names = "ethif","cryp";
26 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;