Merge branch 'spectre' of git://git.armlinux.org.uk/~rmk/linux-arm
[sfrench/cifs-2.6.git] / Documentation / devicetree / bindings / clock / ti / davinci / da8xx-cfgchip.txt
1 Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
2
3 TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
4 registers call CFGCHIPn. Some of these registers function as clock
5 gates. This document describes the bindings for those clocks.
6
7 All of the clock nodes described below must be child nodes of a CFGCHIP node
8 (compatible = "ti,da830-cfgchip").
9
10 USB PHY clocks
11 --------------
12 Required properties:
13 - compatible: shall be "ti,da830-usb-phy-clocks".
14 - #clock-cells: from common clock binding; shall be set to 1.
15 - clocks: phandles to the parent clocks corresponding to clock-names
16 - clock-names: shall be "fck", "usb_refclkin", "auxclk"
17
18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
19 clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
20
21 eHRPWM Time Base Clock (TBCLK)
22 ------------------------------
23 Required properties:
24 - compatible: shall be "ti,da830-tbclksync".
25 - #clock-cells: from common clock binding; shall be set to 0.
26 - clocks: phandle to the parent clock
27 - clock-names: shall be "fck"
28
29 PLL DIV4.5 divider
30 ------------------
31 Required properties:
32 - compatible: shall be "ti,da830-div4p5ena".
33 - #clock-cells: from common clock binding; shall be set to 0.
34 - clocks: phandle to the parent clock
35 - clock-names: shall be "pll0_pllout"
36
37 EMIFA clock source (ASYNC1)
38 ---------------------------
39 Required properties:
40 - compatible: shall be "ti,da850-async1-clksrc".
41 - #clock-cells: from common clock binding; shall be set to 0.
42 - clocks: phandles to the parent clocks corresponding to clock-names
43 - clock-names: shall be "pll0_sysclk3", "div4.5"
44
45 ASYNC3 clock source
46 -------------------
47 Required properties:
48 - compatible: shall be "ti,da850-async3-clksrc".
49 - #clock-cells: from common clock binding; shall be set to 0.
50 - clocks: phandles to the parent clocks corresponding to clock-names
51 - clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
52
53 Examples:
54
55         cfgchip: syscon@1417c {
56                 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
57                 reg = <0x1417c 0x14>;
58
59                 usb_phy_clk: usb-phy-clocks {
60                         compatible = "ti,da830-usb-phy-clocks";
61                         #clock-cells = <1>;
62                         clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
63                         clock-names = "fck", "usb_refclkin", "auxclk";
64                 };
65                 ehrpwm_tbclk: ehrpwm_tbclk {
66                         compatible = "ti,da830-tbclksync";
67                         #clock-cells = <0>;
68                         clocks = <&psc1 17>;
69                         clock-names = "fck";
70                 };
71                 div4p5_clk: div4.5 {
72                         compatible = "ti,da830-div4p5ena";
73                         #clock-cells = <0>;
74                         clocks = <&pll0_pllout>;
75                         clock-names = "pll0_pllout";
76                 };
77                 async1_clk: async1 {
78                         compatible = "ti,da850-async1-clksrc";
79                         #clock-cells = <0>;
80                         clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
81                         clock-names = "pll0_sysclk3", "div4.5";
82                 };
83                 async3_clk: async3 {
84                         compatible = "ti,da850-async3-clksrc";
85                         #clock-cells = <0>;
86                         clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
87                         clock-names = "pll0_sysclk2", "pll1_sysclk2";
88                 };
89         };
90
91 Also see:
92 - Documentation/devicetree/bindings/clock/clock-bindings.txt
93