1 * Renesas R-Car Gen2 Clock Pulse Generator (CPG)
3 The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
4 and several fixed ratio dividers.
8 - compatible: Must be one of
9 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
10 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
11 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
12 - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
14 - reg: Base address and length of the memory resource used by the CPG
16 - clocks: Reference to the parent clock
17 - #clock-cells: Must be 1
18 - clock-output-names: The names of the clocks. Supported clocks are "main",
19 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
25 cpg_clocks: cpg_clocks@e6150000 {
26 compatible = "renesas,r8a7790-cpg-clocks",
27 "renesas,rcar-gen2-cpg-clocks";
28 reg = <0 0xe6150000 0 0x1000>;
29 clocks = <&extal_clk>;
31 clock-output-names = "main", "pll0, "pll1", "pll3",
32 "lb", "qspi", "sdh", "sd0", "sd1", "z";