1 * Clock Block on Freescale QorIQ Platforms
3 Freescale QorIQ chips take primary clocking input from the external
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
6 which can then be passed to a variety of internal logic, including
7 cores and peripheral IP blocks.
8 Please refer to the Reference Manual for details.
10 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11 which the chip complies.
13 Chassis Version Example Chips
14 --------------- -------------
15 1.0 p4080, p5020, p5040
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
31 * "fsl,t1023-clockgen"
32 * "fsl,t1024-clockgen"
33 * "fsl,t1040-clockgen"
34 * "fsl,t1042-clockgen"
35 * "fsl,t2080-clockgen"
36 * "fsl,t2081-clockgen"
37 * "fsl,t4240-clockgen"
38 * "fsl,b4420-clockgen"
39 * "fsl,b4860-clockgen"
40 * "fsl,ls1012a-clockgen"
41 * "fsl,ls1021a-clockgen"
42 * "fsl,ls1043a-clockgen"
43 * "fsl,ls1046a-clockgen"
44 * "fsl,ls1088a-clockgen"
45 * "fsl,ls2080a-clockgen"
46 Chassis-version clock strings include:
47 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
48 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
49 - reg: Describes the address of the device's resources within the
50 address space defined by its parent bus, and resource zero
51 represents the clock register set
54 - ranges: Allows valid translation between child's address space and
55 parent's. Must be present if the device has sub-nodes.
56 - #address-cells: Specifies the number of cells used to represent
57 physical base addresses. Must be present if the device has
58 sub-nodes and set to 1 if present
59 - #size-cells: Specifies the number of cells used to represent
60 the size of an address. Must be present if the device has
61 sub-nodes and set to 1 if present
62 - clock-frequency: Input system clock frequency (SYSCLK)
63 - clocks: If clock-frequency is not specified, sysclk may be provided
64 as an input clock. Either clock-frequency or clocks must be
66 A second input clock, called "coreclk", may be provided if
67 core PLLs are based on a different input clock from the
69 - clock-names: Required if a coreclk is present. Valid names are
70 "sysclk" and "coreclk".
74 The clockgen node should act as a clock provider, though in older device
75 trees the children of the clockgen node are the clock providers.
77 When the clockgen node is a clock provider, #clock-cells = <2>.
78 The first cell of the clock specifier is the clock type, and the
79 second cell is the clock index for the specified type.
83 1 cmux index (n in CLKCnCSR)
84 2 hwaccel index (n in CLKCGnHWACSR)
85 3 fman 0 for fm1, 1 for fm2
86 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
87 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
92 clockgen: global-utilities@e1000 {
93 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
94 clock-frequency = <133333333>;
95 reg = <0xe1000 0x1000>;
101 clocks = <&clockgen 3 0>;
105 4. Legacy Child Nodes
107 NOTE: These nodes are deprecated. Kernels should continue to support
108 device trees with these nodes, but new device trees should not use them.
110 Most of the bindings are from the common clock binding[1].
111 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
114 - compatible : Should include one of the following:
115 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
116 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
117 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
118 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
119 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
120 It takes parent's clock-frequency as its clock.
121 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
122 It takes parent's clock-frequency as its clock.
123 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
124 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
125 - #clock-cells: From common clock binding. The number of cells in a
126 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
127 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
128 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
129 clock-specifier cell may take the following values:
130 * 0 - equal to the PLL frequency
131 * 1 - equal to the PLL frequency divided by 2
132 * 2 - equal to the PLL frequency divided by 4
134 Recommended properties:
135 - clocks: Should be the phandle of input parent clock
136 - clock-names: From common clock binding, indicates the clock name
137 - clock-output-names: From common clock binding, indicates the names of
139 - reg: Should be the offset and length of clock block base address.
140 The length should be 4.
144 clockgen: global-utilities@e1000 {
145 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
146 ranges = <0x0 0xe1000 0x1000>;
147 clock-frequency = <133333333>;
148 reg = <0xe1000 0x1000>;
149 #address-cells = <1>;
154 compatible = "fsl,qoriq-sysclk-1.0";
155 clock-output-names = "sysclk";
161 compatible = "fsl,qoriq-core-pll-1.0";
163 clock-output-names = "pll0", "pll0-div2";
169 compatible = "fsl,qoriq-core-pll-1.0";
171 clock-output-names = "pll1", "pll1-div2";
177 compatible = "fsl,qoriq-core-mux-1.0";
178 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
179 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
180 clock-output-names = "cmux0";
186 compatible = "fsl,qoriq-core-mux-1.0";
187 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
188 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
189 clock-output-names = "cmux1";
192 platform-pll: platform-pll@c00 {
195 compatible = "fsl,qoriq-platform-pll-1.0";
197 clock-output-names = "platform-pll", "platform-pll-div2";
202 Example for legacy clock consumer:
205 cpu0: PowerPC,e5500@0 {