1 * Clock Block on Freescale QorIQ Platforms
3 Freescale QorIQ chips take primary clocking input from the external
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5 multiple phase locked loops (PLL) to create a variety of frequencies
6 which can then be passed to a variety of internal logic, including
7 cores and peripheral IP blocks.
8 Please refer to the Reference Manual for details.
10 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11 which the chip complies.
13 Chassis Version Example Chips
14 --------------- -------------
15 1.0 p4080, p5020, p5040
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
31 * "fsl,t4240-clockgen"
32 * "fsl,b4420-clockgen"
33 * "fsl,b4860-clockgen"
34 * "fsl,ls1012a-clockgen"
35 * "fsl,ls1021a-clockgen"
36 * "fsl,ls1043a-clockgen"
37 * "fsl,ls1046a-clockgen"
38 * "fsl,ls1088a-clockgen"
39 * "fsl,ls2080a-clockgen"
40 Chassis-version clock strings include:
41 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
42 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
43 - reg: Describes the address of the device's resources within the
44 address space defined by its parent bus, and resource zero
45 represents the clock register set
48 - ranges: Allows valid translation between child's address space and
49 parent's. Must be present if the device has sub-nodes.
50 - #address-cells: Specifies the number of cells used to represent
51 physical base addresses. Must be present if the device has
52 sub-nodes and set to 1 if present
53 - #size-cells: Specifies the number of cells used to represent
54 the size of an address. Must be present if the device has
55 sub-nodes and set to 1 if present
56 - clock-frequency: Input system clock frequency (SYSCLK)
57 - clocks: If clock-frequency is not specified, sysclk may be provided
58 as an input clock. Either clock-frequency or clocks must be
63 The clockgen node should act as a clock provider, though in older device
64 trees the children of the clockgen node are the clock providers.
66 When the clockgen node is a clock provider, #clock-cells = <2>.
67 The first cell of the clock specifier is the clock type, and the
68 second cell is the clock index for the specified type.
72 1 cmux index (n in CLKCnCSR)
73 2 hwaccel index (n in CLKCGnHWACSR)
74 3 fman 0 for fm1, 1 for fm2
75 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
79 clockgen: global-utilities@e1000 {
80 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
81 clock-frequency = <133333333>;
82 reg = <0xe1000 0x1000>;
88 clocks = <&clockgen 3 0>;
94 NOTE: These nodes are deprecated. Kernels should continue to support
95 device trees with these nodes, but new device trees should not use them.
97 Most of the bindings are from the common clock binding[1].
98 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
101 - compatible : Should include one of the following:
102 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
103 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
104 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
105 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
106 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
107 It takes parent's clock-frequency as its clock.
108 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
109 It takes parent's clock-frequency as its clock.
110 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
111 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
112 - #clock-cells: From common clock binding. The number of cells in a
113 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
114 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
115 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
116 clock-specifier cell may take the following values:
117 * 0 - equal to the PLL frequency
118 * 1 - equal to the PLL frequency divided by 2
119 * 2 - equal to the PLL frequency divided by 4
121 Recommended properties:
122 - clocks: Should be the phandle of input parent clock
123 - clock-names: From common clock binding, indicates the clock name
124 - clock-output-names: From common clock binding, indicates the names of
126 - reg: Should be the offset and length of clock block base address.
127 The length should be 4.
131 clockgen: global-utilities@e1000 {
132 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
133 ranges = <0x0 0xe1000 0x1000>;
134 clock-frequency = <133333333>;
135 reg = <0xe1000 0x1000>;
136 #address-cells = <1>;
141 compatible = "fsl,qoriq-sysclk-1.0";
142 clock-output-names = "sysclk";
148 compatible = "fsl,qoriq-core-pll-1.0";
150 clock-output-names = "pll0", "pll0-div2";
156 compatible = "fsl,qoriq-core-pll-1.0";
158 clock-output-names = "pll1", "pll1-div2";
164 compatible = "fsl,qoriq-core-mux-1.0";
165 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
166 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
167 clock-output-names = "cmux0";
173 compatible = "fsl,qoriq-core-mux-1.0";
174 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
175 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
176 clock-output-names = "cmux1";
179 platform-pll: platform-pll@c00 {
182 compatible = "fsl,qoriq-platform-pll-1.0";
184 clock-output-names = "platform-pll", "platform-pll-div2";
189 Example for legacy clock consumer:
192 cpu0: PowerPC,e5500@0 {