1 Qualcomm Graphics Clock & Reset Controller Binding
2 --------------------------------------------------
5 - compatible : shall contain "qcom,sdm845-gpucc"
6 - reg : shall contain base register location and length
7 - #clock-cells : from common clock binding, shall contain 1
8 - #reset-cells : from common reset binding, shall contain 1
9 - #power-domain-cells : from generic power domain binding, shall contain 1
10 - clocks : shall contain the XO clock
11 - clock-names : shall be "xo"
14 gpucc: clock-controller@5090000 {
15 compatible = "qcom,sdm845-gpucc";
16 reg = <0x5090000 0x9000>;
19 #power-domain-cells = <1>;
20 clocks = <&rpmhcc RPMH_CXO_CLK>;