1 * Gated Clock bindings for Marvell EBU SoCs
3 Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
4 peripheral clocks to be gated to save some power. The clock consumer
5 should specify the desired clock by having the clock ID in its
6 "clocks" phandle cell. The clock ID is directly mapped to the
7 corresponding clock gating control bit in HW to ease manual clock
10 The following is a list of provided IDs for Armada 370:
12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
16 3 ge1 Gigabit Ethernet 1
17 4 ge0 Gigabit Ethernet 0
22 25 tdm Time Division Mplx
26 The following is a list of provided IDs for Armada 375:
28 -----------------------------------
32 5 pex0 PCIe 0 Clock out
33 6 pex1 PCIe 1 Clock out
35 11 nd_clk Nand Flash Cntrl
36 14 sata0_link SATA 0 Link
37 15 sata0_core SATA 0 Core
41 19 gop Gigabit Ethernet MAC
42 20 sata1_link SATA 1 Link
43 21 sata1_core SATA 1 Core
47 25 tdm Time Division Mplx
48 28 crypto0_enc Cryptographic Unit Port 0 Encryption
49 29 crypto0_core Cryptographic Unit Port 0 Core
50 30 crypto1_enc Cryptographic Unit Port 1 Encryption
51 31 crypto1_core Cryptographic Unit Port 1 Core
53 The following is a list of provided IDs for Armada 380/385:
55 -----------------------------------
57 2 ge2 Gigabit Ethernet 2
58 3 ge1 Gigabit Ethernet 1
59 4 ge0 Gigabit Ethernet 0
67 13 bm Buffer Management
68 14 crypto0z Cryptographic 0 Z
70 16 crypto1z Cryptographic 1 Z
73 21 crypto1 Cryptographic 1
75 23 crypto0 Cryptographic 0
76 25 tdm Time Division Multiplexing
80 The following is a list of provided IDs for Armada XP:
82 -----------------------------------
84 1 ge3 Gigabit Ethernet 3
85 2 ge2 Gigabit Ethernet 2
86 3 ge1 Gigabit Ethernet 1
87 4 ge0 Gigabit Ethernet 0
101 23 crypto CESA engine
102 25 tdm Time Division Mplx
107 The following is a list of provided IDs for Dove:
109 -----------------------------------
112 2 ge Gigabit Ethernet
119 11 camera Camera Cntrl
122 15 crypto CESA engine
124 22 pdma Peripheral DMA
127 30 gephy Gigabit Ethernel PHY
128 Note: gephy(30) is implemented as a parent clock of ge(2)
130 The following is a list of provided IDs for Kirkwood:
132 -----------------------------------
133 0 ge0 Gigabit Ethernet 0
137 5 tsu Transp. Stream Unit
145 17 crypto CESA engine
147 19 ge1 Gigabit Ethernet 1
148 20 tdm Time Division Mplx
151 - compatible : shall be one of the following:
152 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
153 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
154 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
155 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
156 "marvell,dove-gating-clock" - for Dove SoC clock gating
157 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
158 - reg : shall be the register address of the Clock Gating Control register
159 - #clock-cells : from common clock binding; shall be set to 1
162 - clocks : default parent clock phandle (e.g. tclk)
166 gate_clk: clock-gating-control@d0038 {
167 compatible = "marvell,dove-gating-clock";
169 /* default parent clock is tclk */
170 clocks = <&core_clk 0>;
175 compatible = "marvell,dove-sdhci";
176 /* get clk gate bit 8 (sdio0) */
177 clocks = <&gate_clk 8>;