1 Binding for IDT VersaClock5 programmable i2c clock generator.
3 The IDT VersaClock5 are programmable i2c clock generators providing
4 from 3 to 12 output clocks.
9 - compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933".
10 - reg: i2c device address, shall be 0x68 or 0x6a.
11 - #clock-cells: from common clock binding; shall be set to 1.
12 - clocks: from common clock binding; list of parent clock handles,
13 - 5p49v5923: (required) either or both of XTAL or CLKIN
15 - 5p49v5933: (optional) property not present (internal
16 Xtal used) or CLKIN reference
18 - clock-names: from common clock binding; clock input names, can be
19 - 5p49v5923: (required) either or both of "xin", "clkin".
20 - 5p49v5933: (optional) property not present or "clkin".
22 ==Mapping between clock specifier and physical pins==
24 When referencing the provided clock in the DT using phandle and
25 clock specifier, the following mapping applies:
39 /* 25MHz reference crystal */
41 compatible = "fixed-clock";
43 clock-frequency = <25000000>;
48 /* IDT 5P49V5923 i2c clock generator */
49 vc5: clock-generator@6a {
50 compatible = "idt,5p49v5923";
54 /* Connect XIN input to 25MHz reference */
60 /* Consumer referencing the 5P49V5923 pin OUT1 */