1 Binding for IDT VersaClock5 programmable i2c clock generator.
3 The IDT VersaClock5 are programmable i2c clock generators providing
4 from 3 to 12 output clocks.
9 - compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
11 - reg: i2c device address, shall be 0x68 or 0x6a.
12 - #clock-cells: from common clock binding; shall be set to 1.
13 - clocks: from common clock binding; list of parent clock handles,
14 - 5p49v5923: (required) either or both of XTAL or CLKIN
17 - 5p49v5935: (optional) property not present (internal
18 Xtal used) or CLKIN reference
20 - clock-names: from common clock binding; clock input names, can be
21 - 5p49v5923: (required) either or both of "xin", "clkin".
23 - 5p49v5935: (optional) property not present or "clkin".
25 ==Mapping between clock specifier and physical pins==
27 When referencing the provided clock in the DT using phandle and
28 clock specifier, the following mapping applies:
49 /* 25MHz reference crystal */
51 compatible = "fixed-clock";
53 clock-frequency = <25000000>;
58 /* IDT 5P49V5923 i2c clock generator */
59 vc5: clock-generator@6a {
60 compatible = "idt,5p49v5923";
64 /* Connect XIN input to 25MHz reference */
70 /* Consumer referencing the 5P49V5923 pin OUT1 */