Documentation/devicetree/bindings/clock/exynos5433-clock.txt

   1 * Samsung Exynos5433 CMU (Clock Management Units)
   2
   3 The Exynos5433 clock controller generates and supplies clock to various
   4 controllers within the Exynos5433 SoC.
   5
   6 Required Properties:
   7
   8 - compatible: should be one of the following.
   9   - "samsung,exynos5433-cmu-top"   - clock controller compatible for CMU_TOP
  10     which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
  11     domains and bus clocks.
  12   - "samsung,exynos5433-cmu-cpif"  - clock controller compatible for CMU_CPIF
  13     which generates clocks for LLI (Low Latency Interface) IP.
  14   - "samsung,exynos5433-cmu-mif"   - clock controller compatible for CMU_MIF
  15     which generates clocks for DRAM Memory Controller domain.
  16   - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
  17     which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
  18   - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
  19     which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
  20   - "samsung,exynos5433-cmu-fsys"  - clock controller compatible for CMU_FSYS
  21     which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
  22   - "samsung,exynos5433-cmu-g2d"   - clock controller compatible for CMU_G2D
  23     which generates clocks for G2D/MDMA IPs.
  24   - "samsung,exynos5433-cmu-disp"  - clock controller compatible for CMU_DISP
  25     which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
  26   - "samsung,exynos5433-cmu-aud"   - clock controller compatible for CMU_AUD
  27     which generates clocks for Cortex-A5/BUS/AUDIO clocks.
  28   - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
  29     and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
  30     which generates global data buses clock and global peripheral buses clock.
  31   - "samsung,exynos5433-cmu-g3d"  - clock controller compatible for CMU_G3D
  32     which generates clocks for 3D Graphics Engine IP.
  33   - "samsung,exynos5433-cmu-gscl"  - clock controller compatible for CMU_GSCL
  34     which generates clocks for GSCALER IPs.
  35   - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
  36     which generates clocks for Cortex-A53 Quad-core processor.
  37   - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
  38     which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
  39     L2 cache controller.
  40   - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
  41     which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
  42   - "samsung,exynos5433-cmu-mfc"  - clock controller compatible for CMU_MFC
  43     which generates clocks for MFC(Multi-Format Codec) IP.
  44   - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
  45     which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
  46   - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
  47     which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
  48   - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
  49     which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
  50     IPs.
  51   - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
  52     which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
  53
  54 - reg: physical base address of the controller and length of memory mapped
  55   region.
  56
  57 - #clock-cells: should be 1.
  58
  59 - clocks: list of the clock controller input clock identifiers,
  60         from common clock bindings. Please refer the next section
  61         to find the input clocks for a given controller.
  62
  63 - clock-names: list of the clock controller input clock names,
  64         as described in clock-bindings.txt.
  65
  66         Input clocks for top clock controller:
  67                 - oscclk
  68                 - sclk_mphy_pll
  69                 - sclk_mfc_pll
  70                 - sclk_bus_pll
  71
  72         Input clocks for cpif clock controller:
  73                 - oscclk
  74
  75         Input clocks for mif clock controller:
  76                 - oscclk
  77                 - sclk_mphy_pll
  78
  79         Input clocks for fsys clock controller:
  80                 - oscclk
  81                 - sclk_ufs_mphy
  82                 - aclk_fsys_200
  83                 - sclk_pcie_100_fsys
  84                 - sclk_ufsunipro_fsys
  85                 - sclk_mmc2_fsys
  86                 - sclk_mmc1_fsys
  87                 - sclk_mmc0_fsys
  88                 - sclk_usbhost30_fsys
  89                 - sclk_usbdrd30_fsys
  90
  91         Input clocks for g2d clock controller:
  92                 - oscclk
  93                 - aclk_g2d_266
  94                 - aclk_g2d_400
  95
  96         Input clocks for disp clock controller:
  97                 - oscclk
  98                 - sclk_dsim1_disp
  99                 - sclk_dsim0_disp
 100                 - sclk_dsd_disp
 101                 - sclk_decon_tv_eclk_disp
 102                 - sclk_decon_vclk_disp
 103                 - sclk_decon_eclk_disp
 104                 - sclk_decon_tv_vclk_disp
 105                 - aclk_disp_333
 106
 107         Input clocks for audio clock controller:
 108                 - oscclk
 109                 - fout_aud_pll
 110
 111         Input clocks for bus0 clock controller:
 112                 - aclk_bus0_400
 113
 114         Input clocks for bus1 clock controller:
 115                 - aclk_bus1_400
 116
 117         Input clocks for bus2 clock controller:
 118                 - oscclk
 119                 - aclk_bus2_400
 120
 121         Input clocks for g3d clock controller:
 122                 - oscclk
 123                 - aclk_g3d_400
 124
 125         Input clocks for gscl clock controller:
 126                 - oscclk
 127                 - aclk_gscl_111
 128                 - aclk_gscl_333
 129
 130         Input clocks for apollo clock controller:
 131                 - oscclk
 132                 - sclk_bus_pll_apollo
 133
 134         Input clocks for atlas clock controller:
 135                 - oscclk
 136                 - sclk_bus_pll_atlas
 137
 138         Input clocks for mscl clock controller:
 139                 - oscclk
 140                 - sclk_jpeg_mscl
 141                 - aclk_mscl_400
 142
 143         Input clocks for mfc clock controller:
 144                 - oscclk
 145                 - aclk_mfc_400
 146
 147         Input clocks for hevc clock controller:
 148                 - oscclk
 149                 - aclk_hevc_400
 150
 151         Input clocks for isp clock controller:
 152                 - oscclk
 153                 - aclk_isp_dis_400
 154                 - aclk_isp_400
 155
 156         Input clocks for cam0 clock controller:
 157                 - oscclk
 158                 - aclk_cam0_333
 159                 - aclk_cam0_400
 160                 - aclk_cam0_552
 161
 162         Input clocks for cam1 clock controller:
 163                 - oscclk
 164                 - sclk_isp_uart_cam1
 165                 - sclk_isp_spi1_cam1
 166                 - sclk_isp_spi0_cam1
 167                 - aclk_cam1_333
 168                 - aclk_cam1_400
 169                 - aclk_cam1_552
 170
 171 Each clock is assigned an identifier and client nodes can use this identifier
 172 to specify the clock which they consume.
 173
 174 All available clocks are defined as preprocessor macros in
 175 dt-bindings/clock/exynos5433.h header and can be used in device
 176 tree sources.
 177
 178 Example 1: Examples of 'oscclk' source clock node are listed below.
 179
 180         xxti: xxti {
 181                 compatible = "fixed-clock";
 182                 clock-output-names = "oscclk";
 183                 #clock-cells = <0>;
 184         };
 185
 186 Example 2: Examples of clock controller nodes are listed below.
 187
 188         cmu_top: clock-controller@10030000 {
 189                 compatible = "samsung,exynos5433-cmu-top";
 190                 reg = <0x10030000 0x0c04>;
 191                 #clock-cells = <1>;
 192
 193                 clock-names = "oscclk",
 194                         "sclk_mphy_pll",
 195                         "sclk_mfc_pll",
 196                         "sclk_bus_pll";
 197                 clocks = <&xxti>,
 198                        <&cmu_cpif CLK_SCLK_MPHY_PLL>,
 199                        <&cmu_mif CLK_SCLK_MFC_PLL>,
 200                        <&cmu_mif CLK_SCLK_BUS_PLL>;
 201         };
 202
 203         cmu_cpif: clock-controller@10fc0000 {
 204                 compatible = "samsung,exynos5433-cmu-cpif";
 205                 reg = <0x10fc0000 0x0c04>;
 206                 #clock-cells = <1>;
 207
 208                 clock-names = "oscclk";
 209                 clocks = <&xxti>;
 210         };
 211
 212         cmu_mif: clock-controller@105b0000 {
 213                 compatible = "samsung,exynos5433-cmu-mif";
 214                 reg = <0x105b0000 0x100c>;
 215                 #clock-cells = <1>;
 216
 217                 clock-names = "oscclk",
 218                         "sclk_mphy_pll";
 219                 clocks = <&xxti>,
 220                        <&cmu_cpif CLK_SCLK_MPHY_PLL>;
 221         };
 222
 223         cmu_peric: clock-controller@14c80000 {
 224                 compatible = "samsung,exynos5433-cmu-peric";
 225                 reg = <0x14c80000 0x0b08>;
 226                 #clock-cells = <1>;
 227         };
 228
 229         cmu_peris: clock-controller@10040000 {
 230                 compatible = "samsung,exynos5433-cmu-peris";
 231                 reg = <0x10040000 0x0b20>;
 232                 #clock-cells = <1>;
 233         };
 234
 235         cmu_fsys: clock-controller@156e0000 {
 236                 compatible = "samsung,exynos5433-cmu-fsys";
 237                 reg = <0x156e0000 0x0b04>;
 238                 #clock-cells = <1>;
 239
 240                 clock-names = "oscclk",
 241                         "sclk_ufs_mphy",
 242                         "aclk_fsys_200",
 243                         "sclk_pcie_100_fsys",
 244                         "sclk_ufsunipro_fsys",
 245                         "sclk_mmc2_fsys",
 246                         "sclk_mmc1_fsys",
 247                         "sclk_mmc0_fsys",
 248                         "sclk_usbhost30_fsys",
 249                         "sclk_usbdrd30_fsys";
 250                 clocks = <&xxti>,
 251                        <&cmu_cpif CLK_SCLK_UFS_MPHY>,
 252                        <&cmu_top CLK_ACLK_FSYS_200>,
 253                        <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 254                        <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 255                        <&cmu_top CLK_SCLK_MMC2_FSYS>,
 256                        <&cmu_top CLK_SCLK_MMC1_FSYS>,
 257                        <&cmu_top CLK_SCLK_MMC0_FSYS>,
 258                        <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 259                        <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
 260         };
 261
 262         cmu_g2d: clock-controller@12460000 {
 263                 compatible = "samsung,exynos5433-cmu-g2d";
 264                 reg = <0x12460000 0x0b08>;
 265                 #clock-cells = <1>;
 266
 267                 clock-names = "oscclk",
 268                         "aclk_g2d_266",
 269                         "aclk_g2d_400";
 270                 clocks = <&xxti>,
 271                        <&cmu_top CLK_ACLK_G2D_266>,
 272                        <&cmu_top CLK_ACLK_G2D_400>;
 273         };
 274
 275         cmu_disp: clock-controller@13b90000 {
 276                 compatible = "samsung,exynos5433-cmu-disp";
 277                 reg = <0x13b90000 0x0c04>;
 278                 #clock-cells = <1>;
 279
 280                 clock-names = "oscclk",
 281                         "sclk_dsim1_disp",
 282                         "sclk_dsim0_disp",
 283                         "sclk_dsd_disp",
 284                         "sclk_decon_tv_eclk_disp",
 285                         "sclk_decon_vclk_disp",
 286                         "sclk_decon_eclk_disp",
 287                         "sclk_decon_tv_vclk_disp",
 288                         "aclk_disp_333";
 289                 clocks = <&xxti>,
 290                        <&cmu_mif CLK_SCLK_DSIM1_DISP>,
 291                        <&cmu_mif CLK_SCLK_DSIM0_DISP>,
 292                        <&cmu_mif CLK_SCLK_DSD_DISP>,
 293                        <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 294                        <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
 295                        <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 296                        <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 297                        <&cmu_mif CLK_ACLK_DISP_333>;
 298         };
 299
 300         cmu_aud: clock-controller@114c0000 {
 301                 compatible = "samsung,exynos5433-cmu-aud";
 302                 reg = <0x114c0000 0x0b04>;
 303                 #clock-cells = <1>;
 304
 305                 clock-names = "oscclk", "fout_aud_pll";
 306                 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
 307         };
 308
 309         cmu_bus0: clock-controller@13600000 {
 310                 compatible = "samsung,exynos5433-cmu-bus0";
 311                 reg = <0x13600000 0x0b04>;
 312                 #clock-cells = <1>;
 313
 314                 clock-names = "aclk_bus0_400";
 315                 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
 316         };
 317
 318         cmu_bus1: clock-controller@14800000 {
 319                 compatible = "samsung,exynos5433-cmu-bus1";
 320                 reg = <0x14800000 0x0b04>;
 321                 #clock-cells = <1>;
 322
 323                 clock-names = "aclk_bus1_400";
 324                 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
 325         };
 326
 327         cmu_bus2: clock-controller@13400000 {
 328                 compatible = "samsung,exynos5433-cmu-bus2";
 329                 reg = <0x13400000 0x0b04>;
 330                 #clock-cells = <1>;
 331
 332                 clock-names = "oscclk", "aclk_bus2_400";
 333                 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
 334         };
 335
 336         cmu_g3d: clock-controller@14aa0000 {
 337                 compatible = "samsung,exynos5433-cmu-g3d";
 338                 reg = <0x14aa0000 0x1000>;
 339                 #clock-cells = <1>;
 340
 341                 clock-names = "oscclk", "aclk_g3d_400";
 342                 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
 343         };
 344
 345         cmu_gscl: clock-controller@13cf0000 {
 346                 compatible = "samsung,exynos5433-cmu-gscl";
 347                 reg = <0x13cf0000 0x0b10>;
 348                 #clock-cells = <1>;
 349
 350                 clock-names = "oscclk",
 351                         "aclk_gscl_111",
 352                         "aclk_gscl_333";
 353                 clocks = <&xxti>,
 354                         <&cmu_top CLK_ACLK_GSCL_111>,
 355                         <&cmu_top CLK_ACLK_GSCL_333>;
 356         };
 357
 358         cmu_apollo: clock-controller@11900000 {
 359                 compatible = "samsung,exynos5433-cmu-apollo";
 360                 reg = <0x11900000 0x1088>;
 361                 #clock-cells = <1>;
 362
 363                 clock-names = "oscclk", "sclk_bus_pll_apollo";
 364                 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
 365         };
 366
 367         cmu_atlas: clock-controller@11800000 {
 368                 compatible = "samsung,exynos5433-cmu-atlas";
 369                 reg = <0x11800000 0x1088>;
 370                 #clock-cells = <1>;
 371
 372                 clock-names = "oscclk", "sclk_bus_pll_atlas";
 373                 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
 374         };
 375
 376         cmu_mscl: clock-controller@105d0000 {
 377                 compatible = "samsung,exynos5433-cmu-mscl";
 378                 reg = <0x105d0000 0x0b10>;
 379                 #clock-cells = <1>;
 380
 381                 clock-names = "oscclk",
 382                         "sclk_jpeg_mscl",
 383                         "aclk_mscl_400";
 384                 clocks = <&xxti>,
 385                        <&cmu_top CLK_SCLK_JPEG_MSCL>,
 386                        <&cmu_top CLK_ACLK_MSCL_400>;
 387         };
 388
 389         cmu_mfc: clock-controller@15280000 {
 390                 compatible = "samsung,exynos5433-cmu-mfc";
 391                 reg = <0x15280000 0x0b08>;
 392                 #clock-cells = <1>;
 393
 394                 clock-names = "oscclk", "aclk_mfc_400";
 395                 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
 396         };
 397
 398         cmu_hevc: clock-controller@14f80000 {
 399                 compatible = "samsung,exynos5433-cmu-hevc";
 400                 reg = <0x14f80000 0x0b08>;
 401                 #clock-cells = <1>;
 402
 403                 clock-names = "oscclk", "aclk_hevc_400";
 404                 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
 405         };
 406
 407         cmu_isp: clock-controller@146d0000 {
 408                 compatible = "samsung,exynos5433-cmu-isp";
 409                 reg = <0x146d0000 0x0b0c>;
 410                 #clock-cells = <1>;
 411
 412                 clock-names = "oscclk",
 413                         "aclk_isp_dis_400",
 414                         "aclk_isp_400";
 415                 clocks = <&xxti>,
 416                        <&cmu_top CLK_ACLK_ISP_DIS_400>,
 417                        <&cmu_top CLK_ACLK_ISP_400>;
 418         };
 419
 420         cmu_cam0: clock-controller@120d0000 {
 421                 compatible = "samsung,exynos5433-cmu-cam0";
 422                 reg = <0x120d0000 0x0b0c>;
 423                 #clock-cells = <1>;
 424
 425                 clock-names = "oscclk",
 426                         "aclk_cam0_333",
 427                         "aclk_cam0_400",
 428                         "aclk_cam0_552";
 429                 clocks = <&xxti>,
 430                        <&cmu_top CLK_ACLK_CAM0_333>,
 431                        <&cmu_top CLK_ACLK_CAM0_400>,
 432                        <&cmu_top CLK_ACLK_CAM0_552>;
 433         };
 434
 435         cmu_cam1: clock-controller@145d0000 {
 436                 compatible = "samsung,exynos5433-cmu-cam1";
 437                 reg = <0x145d0000 0x0b08>;
 438                 #clock-cells = <1>;
 439
 440                 clock-names = "oscclk",
 441                         "sclk_isp_uart_cam1",
 442                         "sclk_isp_spi1_cam1",
 443                         "sclk_isp_spi0_cam1",
 444                         "aclk_cam1_333",
 445                         "aclk_cam1_400",
 446                         "aclk_cam1_552";
 447                 clocks = <&xxti>,
 448                        <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
 449                        <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
 450                        <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
 451                        <&cmu_top CLK_ACLK_CAM1_333>,
 452                        <&cmu_top CLK_ACLK_CAM1_400>,
 453                        <&cmu_top CLK_ACLK_CAM1_552>;
 454         };
 455
 456 Example 3: UART controller node that consumes the clock generated by the clock
 457            controller.
 458
 459         serial_0: serial@14C10000 {
 460                 compatible = "samsung,exynos5433-uart";
 461                 reg = <0x14C10000 0x100>;
 462                 interrupts = <0 421 0>;
 463                 clocks = <&cmu_peric CLK_PCLK_UART0>,
 464                          <&cmu_peric CLK_SCLK_UART0>;
 465                 clock-names = "uart", "clk_uart_baud0";
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&uart0_bus>;
 468         };