Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt

   1 Broadcom iProc Family Clocks
   2
   3 This binding uses the common clock binding:
   4     Documentation/devicetree/bindings/clock/clock-bindings.txt
   5
   6 The iProc clock controller manages clocks that are common to the iProc family.
   7 An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
   8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
   9 comprises of several leaf clocks
  10
  11 Required properties for a PLL and its leaf clocks:
  12
  13 - compatible:
  14     Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
  15 Cygnus has a compatible string of "brcm,cygnus-genpll"
  16
  17 - #clock-cells:
  18     Have a value of <1> since there are more than 1 leaf clock of a given PLL
  19
  20 - reg:
  21     Define the base and range of the I/O address space that contain the iProc
  22 clock control registers required for the PLL
  23
  24 - clocks:
  25     The input parent clock phandle for the PLL. For most iProc PLLs, this is an
  26 onboard crystal with a fixed rate
  27
  28 - clock-output-names:
  29     An ordered list of strings defining the names of the clocks
  30
  31 Example:
  32
  33         osc: oscillator {
  34                 #clock-cells = <0>;
  35                 compatible = "fixed-clock";
  36                 clock-frequency = <25000000>;
  37         };
  38
  39         genpll: genpll {
  40                 #clock-cells = <1>;
  41                 compatible = "brcm,cygnus-genpll";
  42                 reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
  43                 clocks = <&osc>;
  44                 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
  45                                      "enet_sw", "audio_125", "can";
  46         };
  47
  48 Required properties for ASIU clocks:
  49
  50 ASIU clocks are a special case. These clocks are derived directly from the
  51 reference clock of the onboard crystal
  52
  53 - compatible:
  54     Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
  55 clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
  56
  57 - #clock-cells:
  58     Have a value of <1> since there are more than 1 ASIU clocks
  59
  60 - reg:
  61     Define the base and range of the I/O address space that contain the iProc
  62 clock control registers required for ASIU clocks
  63
  64 - clocks:
  65     The input parent clock phandle for the ASIU clock, i.e., the onboard
  66 crystal
  67
  68 - clock-output-names:
  69     An ordered list of strings defining the names of the ASIU clocks
  70
  71 Example:
  72
  73         osc: oscillator {
  74                 #clock-cells = <0>;
  75                 compatible = "fixed-clock";
  76                 clock-frequency = <25000000>;
  77         };
  78
  79         asiu_clks: asiu_clks {
  80                 #clock-cells = <1>;
  81                 compatible = "brcm,cygnus-asiu-clk";
  82                 reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
  83                 clocks = <&osc>;
  84                 clock-output-names = "keypad", "adc/touch", "pwm";
  85         };
  86
  87 Cygnus
  88 ------
  89 PLL and leaf clock compatible strings for Cygnus are:
  90     "brcm,cygnus-armpll"
  91     "brcm,cygnus-genpll"
  92     "brcm,cygnus-lcpll0"
  93     "brcm,cygnus-mipipll"
  94     "brcm,cygnus-asiu-clk"
  95     "brcm,cygnus-audiopll"
  96
  97 The following table defines the set of PLL/clock index and ID for Cygnus.
  98 These clock IDs are defined in:
  99     "include/dt-bindings/clock/bcm-cygnus.h"
 100
 101     Clock      Source (Parent)  Index   ID
 102     ---        -----            -----   ---------
 103     crystal    N/A              N/A     N/A
 104
 105     armpll     crystal          N/A     N/A
 106
 107     keypad     crystal (ASIU)   0       BCM_CYGNUS_ASIU_KEYPAD_CLK
 108     adc/tsc    crystal (ASIU)   1       BCM_CYGNUS_ASIU_ADC_CLK
 109     pwm        crystal (ASIU)   2       BCM_CYGNUS_ASIU_PWM_CLK
 110
 111     genpll     crystal          0       BCM_CYGNUS_GENPLL
 112     axi21      genpll           1       BCM_CYGNUS_GENPLL_AXI21_CLK
 113     250mhz     genpll           2       BCM_CYGNUS_GENPLL_250MHZ_CLK
 114     ihost_sys  genpll           3       BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
 115     enet_sw    genpll           4       BCM_CYGNUS_GENPLL_ENET_SW_CLK
 116     audio_125  genpll           5       BCM_CYGNUS_GENPLL_AUDIO_125_CLK
 117     can        genpll           6       BCM_CYGNUS_GENPLL_CAN_CLK
 118
 119     lcpll0     crystal          0       BCM_CYGNUS_LCPLL0
 120     pcie_phy   lcpll0           1       BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
 121     ddr_phy    lcpll0           2       BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
 122     sdio       lcpll0           3       BCM_CYGNUS_LCPLL0_SDIO_CLK
 123     usb_phy    lcpll0           4       BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
 124     smart_card lcpll0           5       BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
 125     ch5_unused lcpll0           6       BCM_CYGNUS_LCPLL0_CH5_UNUSED
 126
 127     mipipll    crystal          0       BCM_CYGNUS_MIPIPLL
 128     ch0_unused mipipll          1       BCM_CYGNUS_MIPIPLL_CH0_UNUSED
 129     ch1_lcd    mipipll          2       BCM_CYGNUS_MIPIPLL_CH1_LCD
 130     ch2_v3d    mipipll          3       BCM_CYGNUS_MIPIPLL_CH2_V3D
 131     ch3_unused mipipll          4       BCM_CYGNUS_MIPIPLL_CH3_UNUSED
 132     ch4_unused mipipll          5       BCM_CYGNUS_MIPIPLL_CH4_UNUSED
 133     ch5_unused mipipll          6       BCM_CYGNUS_MIPIPLL_CH5_UNUSED
 134
 135     audiopll   crystal          0       BCM_CYGNUS_AUDIOPLL
 136     ch0_audio  audiopll         1       BCM_CYGNUS_AUDIOPLL_CH0
 137     ch1_audio  audiopll         2       BCM_CYGNUS_AUDIOPLL_CH1
 138     ch2_audio  audiopll         3       BCM_CYGNUS_AUDIOPLL_CH2
 139
 140 Hurricane 2
 141 ------
 142 PLL and leaf clock compatible strings for Hurricane 2 are:
 143  "brcm,hr2-armpll"
 144
 145 The following table defines the set of PLL/clock for Hurricane 2:
 146
 147     Clock       Source          Index   ID
 148     ---         -----           -----   ---------
 149     crystal     N/A             N/A     N/A
 150
 151     armpll      crystal         N/A     N/A
 152
 153
 154 Northstar and Northstar Plus
 155 ------
 156 PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
 157  "brcm,nsp-armpll"
 158  "brcm,nsp-genpll"
 159  "brcm,nsp-lcpll0"
 160
 161 The following table defines the set of PLL/clock index and ID for Northstar and
 162 Northstar Plus.  These clock IDs are defined in:
 163     "include/dt-bindings/clock/bcm-nsp.h"
 164
 165     Clock       Source          Index   ID
 166     ---         -----           -----   ---------
 167     crystal     N/A             N/A     N/A
 168
 169     armpll      crystal         N/A     N/A
 170
 171     genpll      crystal         0       BCM_NSP_GENPLL
 172     phy         genpll          1       BCM_NSP_GENPLL_PHY_CLK
 173     ethernetclk genpll          2       BCM_NSP_GENPLL_ENET_SW_CLK
 174     usbclk      genpll          3       BCM_NSP_GENPLL_USB_PHY_REF_CLK
 175     iprocfast   genpll          4       BCM_NSP_GENPLL_IPROCFAST_CLK
 176     sata1       genpll          5       BCM_NSP_GENPLL_SATA1_CLK
 177     sata2       genpll          6       BCM_NSP_GENPLL_SATA2_CLK
 178
 179     lcpll0      crystal         0       BCM_NSP_LCPLL0
 180     pcie_phy    lcpll0          1       BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
 181     sdio        lcpll0          2       BCM_NSP_LCPLL0_SDIO_CLK
 182     ddr_phy     lcpll0          3       BCM_NSP_LCPLL0_DDR_PHY_CLK
 183
 184 Northstar 2
 185 -----------
 186 PLL and leaf clock compatible strings for Northstar 2 are:
 187     "brcm,ns2-genpll-scr"
 188     "brcm,ns2-genpll-sw"
 189     "brcm,ns2-lcpll-ddr"
 190     "brcm,ns2-lcpll-ports"
 191
 192 The following table defines the set of PLL/clock index and ID for Northstar 2.
 193 These clock IDs are defined in:
 194     "include/dt-bindings/clock/bcm-ns2.h"
 195
 196     Clock       Source          Index   ID
 197     ---         -----           -----   ---------
 198     crystal     N/A             N/A     N/A
 199
 200     genpll_scr  crystal         0       BCM_NS2_GENPLL_SCR
 201     scr         genpll_scr      1       BCM_NS2_GENPLL_SCR_SCR_CLK
 202     fs          genpll_scr      2       BCM_NS2_GENPLL_SCR_FS_CLK
 203     audio_ref   genpll_scr      3       BCM_NS2_GENPLL_SCR_AUDIO_CLK
 204     ch3_unused  genpll_scr      4       BCM_NS2_GENPLL_SCR_CH3_UNUSED
 205     ch4_unused  genpll_scr      5       BCM_NS2_GENPLL_SCR_CH4_UNUSED
 206     ch5_unused  genpll_scr      6       BCM_NS2_GENPLL_SCR_CH5_UNUSED
 207
 208     genpll_sw   crystal         0       BCM_NS2_GENPLL_SW
 209     rpe         genpll_sw       1       BCM_NS2_GENPLL_SW_RPE_CLK
 210     250         genpll_sw       2       BCM_NS2_GENPLL_SW_250_CLK
 211     nic         genpll_sw       3       BCM_NS2_GENPLL_SW_NIC_CLK
 212     chimp       genpll_sw       4       BCM_NS2_GENPLL_SW_CHIMP_CLK
 213     port        genpll_sw       5       BCM_NS2_GENPLL_SW_PORT_CLK
 214     sdio        genpll_sw       6       BCM_NS2_GENPLL_SW_SDIO_CLK
 215
 216     lcpll_ddr   crystal         0       BCM_NS2_LCPLL_DDR
 217     pcie_sata_usb lcpll_ddr     1       BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
 218     ddr         lcpll_ddr       2       BCM_NS2_LCPLL_DDR_DDR_CLK
 219     ch2_unused  lcpll_ddr       3       BCM_NS2_LCPLL_DDR_CH2_UNUSED
 220     ch3_unused  lcpll_ddr       4       BCM_NS2_LCPLL_DDR_CH3_UNUSED
 221     ch4_unused  lcpll_ddr       5       BCM_NS2_LCPLL_DDR_CH4_UNUSED
 222     ch5_unused  lcpll_ddr       6       BCM_NS2_LCPLL_DDR_CH5_UNUSED
 223
 224     lcpll_ports crystal         0       BCM_NS2_LCPLL_PORTS
 225     wan         lcpll_ports     1       BCM_NS2_LCPLL_PORTS_WAN_CLK
 226     rgmii       lcpll_ports     2       BCM_NS2_LCPLL_PORTS_RGMII_CLK
 227     ch2_unused  lcpll_ports     3       BCM_NS2_LCPLL_PORTS_CH2_UNUSED
 228     ch3_unused  lcpll_ports     4       BCM_NS2_LCPLL_PORTS_CH3_UNUSED
 229     ch4_unused  lcpll_ports     5       BCM_NS2_LCPLL_PORTS_CH4_UNUSED
 230     ch5_unused  lcpll_ports     6       BCM_NS2_LCPLL_PORTS_CH5_UNUSED
 231
 232 BCM63138
 233 --------
 234 PLL and leaf clock compatible strings for BCM63138 are:
 235     "brcm,bcm63138-armpll"
 236
 237 Stingray
 238 -----------
 239 PLL and leaf clock compatible strings for Stingray are:
 240     "brcm,sr-genpll0"
 241     "brcm,sr-genpll1"
 242     "brcm,sr-genpll2"
 243     "brcm,sr-genpll3"
 244     "brcm,sr-genpll4"
 245     "brcm,sr-genpll5"
 246     "brcm,sr-genpll6"
 247
 248     "brcm,sr-lcpll0"
 249     "brcm,sr-lcpll1"
 250     "brcm,sr-lcpll-pcie"
 251
 252
 253 The following table defines the set of PLL/clock index and ID for Stingray.
 254 These clock IDs are defined in:
 255     "include/dt-bindings/clock/bcm-sr.h"
 256
 257     Clock               Source          Index   ID
 258     ---                 -----           -----   ---------
 259     crystal             N/A             N/A     N/A
 260     crmu_ref25m         crystal         N/A     N/A
 261
 262     genpll0             crystal         0       BCM_SR_GENPLL0
 263     clk_125m            genpll0         1       BCM_SR_GENPLL0_125M_CLK
 264     clk_scr             genpll0         2       BCM_SR_GENPLL0_SCR_CLK
 265     clk_250             genpll0         3       BCM_SR_GENPLL0_250M_CLK
 266     clk_pcie_axi        genpll0         4       BCM_SR_GENPLL0_PCIE_AXI_CLK
 267     clk_paxc_axi_x2     genpll0         5       BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
 268     clk_paxc_axi        genpll0         6       BCM_SR_GENPLL0_PAXC_AXI_CLK
 269
 270     genpll1             crystal         0       BCM_SR_GENPLL1
 271     clk_pcie_tl         genpll1         1       BCM_SR_GENPLL1_PCIE_TL_CLK
 272     clk_mhb_apb         genpll1         2       BCM_SR_GENPLL1_MHB_APB_CLK
 273
 274     genpll2             crystal         0       BCM_SR_GENPLL2
 275     clk_nic             genpll2         1       BCM_SR_GENPLL2_NIC_CLK
 276     clk_ts_500_ref      genpll2         2       BCM_SR_GENPLL2_TS_500_REF_CLK
 277     clk_125_nitro       genpll2         3       BCM_SR_GENPLL2_125_NITRO_CLK
 278     clk_chimp           genpll2         4       BCM_SR_GENPLL2_CHIMP_CLK
 279     clk_nic_flash       genpll2         5       BCM_SR_GENPLL2_NIC_FLASH
 280
 281     genpll3             crystal         0       BCM_SR_GENPLL3
 282     clk_hsls            genpll3         1       BCM_SR_GENPLL3_HSLS_CLK
 283     clk_sdio            genpll3         2       BCM_SR_GENPLL3_SDIO_CLK
 284
 285     genpll4             crystal         0       BCM_SR_GENPLL4
 286     ccn                 genpll4         1       BCM_SR_GENPLL4_CCN_CLK
 287     clk_tpiu_pll        genpll4         2       BCM_SR_GENPLL4_TPIU_PLL_CLK
 288     noc_clk             genpll4         3       BCM_SR_GENPLL4_NOC_CLK
 289     clk_chclk_fs4       genpll4         4       BCM_SR_GENPLL4_CHCLK_FS4_CLK
 290     clk_bridge_fscpu    genpll4         5       BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
 291
 292
 293     genpll5             crystal         0       BCM_SR_GENPLL5
 294     fs4_hf_clk          genpll5         1       BCM_SR_GENPLL5_FS4_HF_CLK
 295     crypto_ae_clk       genpll5         2       BCM_SR_GENPLL5_CRYPTO_AE_CLK
 296     raid_ae_clk         genpll5         3       BCM_SR_GENPLL5_RAID_AE_CLK
 297
 298     genpll6             crystal         0       BCM_SR_GENPLL6
 299     48_usb              genpll6         1       BCM_SR_GENPLL6_48_USB_CLK
 300
 301     lcpll0              crystal         0       BCM_SR_LCPLL0
 302     clk_sata_refp       lcpll0          1       BCM_SR_LCPLL0_SATA_REFP_CLK
 303     clk_sata_refn       lcpll0          2       BCM_SR_LCPLL0_SATA_REFN_CLK
 304     clk_usb_ref         lcpll0          3       BCM_SR_LCPLL0_USB_REF_CLK
 305     sata_refpn          lcpll0          3       BCM_SR_LCPLL0_SATA_REFPN_CLK
 306
 307     lcpll1              crystal         0       BCM_SR_LCPLL1
 308     wan                 lcpll1          1       BCM_SR_LCPLL0_WAN_CLK
 309
 310     lcpll_pcie          crystal         0       BCM_SR_LCPLL_PCIE
 311     pcie_phy_ref        lcpll1          1       BCM_SR_LCPLL_PCIE_PHY_REF_CLK