Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

   1 * Amlogic AXG Audio Clock Controllers
   2
   3 The Amlogic AXG audio clock controller generates and supplies clock to the
   4 other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
   5 devices.
   6
   7 Required Properties:
   8
   9 - compatible    : should be "amlogic,axg-audio-clkc" for the A113X and A113D
  10 - reg           : physical base address of the clock controller and length of
  11                   memory mapped region.
  12 - clocks        : a list of phandle + clock-specifier pairs for the clocks listed
  13                   in clock-names.
  14 - clock-names   : must contain the following:
  15                   * "pclk" - Main peripheral bus clock
  16                   may contain the following:
  17                   * "mst_in[0-7]" - 8 input plls to generate clock signals
  18                   * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
  19                                       components.
  20                   * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
  21                                        components.
  22 - resets        : phandle of the internal reset line
  23 - #clock-cells  : should be 1.
  24
  25 Each clock is assigned an identifier and client nodes can use this identifier
  26 to specify the clock which they consume. All available clocks are defined as
  27 preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
  28 used in device tree sources.
  29
  30 Example:
  31
  32 clkc_audio: clock-controller@0 {
  33         compatible = "amlogic,axg-audio-clkc";
  34         reg = <0x0 0x0 0x0 0xb4>;
  35         #clock-cells = <1>;
  36
  37         clocks = <&clkc CLKID_AUDIO>,
  38                  <&clkc CLKID_MPLL0>,
  39                  <&clkc CLKID_MPLL1>,
  40                  <&clkc CLKID_MPLL2>,
  41                  <&clkc CLKID_MPLL3>,
  42                  <&clkc CLKID_HIFI_PLL>,
  43                  <&clkc CLKID_FCLK_DIV3>,
  44                  <&clkc CLKID_FCLK_DIV4>,
  45                  <&clkc CLKID_GP0_PLL>;
  46         clock-names = "pclk",
  47                       "mst_in0",
  48                       "mst_in1",
  49                       "mst_in2",
  50                       "mst_in3",
  51                       "mst_in4",
  52                       "mst_in5",
  53                       "mst_in6",
  54                       "mst_in7";
  55         resets = <&reset RESET_AUDIO>;
  56 };