1 * Amlogic AXG Audio Clock Controllers
3 The Amlogic AXG audio clock controller generates and supplies clock to the
4 other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
9 - compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
10 "amlogic,g12a-audio-clkc" for G12A.
11 - reg : physical base address of the clock controller and length of
13 - clocks : a list of phandle + clock-specifier pairs for the clocks listed
15 - clock-names : must contain the following:
16 * "pclk" - Main peripheral bus clock
17 may contain the following:
18 * "mst_in[0-7]" - 8 input plls to generate clock signals
19 * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
21 * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
23 - resets : phandle of the internal reset line
24 - #clock-cells : should be 1.
25 - #reset-cells : should be 1 on the g12a (and following) soc family
27 Each clock is assigned an identifier and client nodes can use this identifier
28 to specify the clock which they consume. All available clocks are defined as
29 preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
30 used in device tree sources.
34 clkc_audio: clock-controller@0 {
35 compatible = "amlogic,axg-audio-clkc";
36 reg = <0x0 0x0 0x0 0xb4>;
39 clocks = <&clkc CLKID_AUDIO>,
44 <&clkc CLKID_HIFI_PLL>,
45 <&clkc CLKID_FCLK_DIV3>,
46 <&clkc CLKID_FCLK_DIV4>,
47 <&clkc CLKID_GP0_PLL>;
57 resets = <&reset RESET_AUDIO>;