1 Texas Instruments sysc interconnect target module wrapper binding
3 Texas Instruments SoCs can have a generic interconnect target module
4 hardware for devices connected to various interconnects such as L3
5 interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
6 is mostly used for interaction between module and PRCM. It participates
7 in the OCP Disconnect Protocol but other than that is mostly independent
10 Each interconnect target module can have one or more devices connected to
11 it. There is a set of control registers for managing interconnect target
12 module clocks, idle modes and interconnect level resets for the module.
14 These control registers are sprinkled into the unused register address
15 space of the first child device IP block managed by the interconnect
16 target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.
18 Required standard properties:
20 - compatible shall be one of the following generic types:
25 "ti,sysc-omap4-simple"
27 or one of the following derivative types for hardware
28 needing special workarounds:
41 - reg shall have register areas implemented for the interconnect
42 target module in question such as revision, sysc and syss
44 - reg-names shall contain the register names implemented for the
45 interconnect target module in question such as
46 "rev, "sysc", and "syss"
48 - ranges shall contain the interconnect target module IO range
49 available for one or more child device IP blocks managed
50 by the interconnect target module, the ranges may include
51 multiple ranges such as device L4 range for control and
52 parent L3 range for DMA access
56 - ti,sysc-mask shall contain mask of supported register bits for the
57 SYSCONFIG register as documented in the Technical Reference
58 Manual (TRM) for the interconnect target module
60 - ti,sysc-midle list of master idle modes supported by the interconnect
61 target module as documented in the TRM for SYSCONFIG
62 register MIDLEMODE bits
64 - ti,sysc-sidle list of slave idle modes supported by the interconnect
65 target module as documented in the TRM for SYSCONFIG
66 register SIDLEMODE bits
68 - ti,sysc-delay-us delay needed after OCP softreset before accssing
69 SYSCONFIG register again
71 - ti,syss-mask optional mask of reset done status bits as described in the
72 TRM for SYSSTATUS registers, typically 1 with some devices
73 having separate reset done bits for children like OHCI and
76 - clocks clock specifier for each name in the clock-names as
77 specified in the binding documentation for ti-clkctrl,
78 typically available for all interconnect targets on TI SoCs
79 based on omap4 except if it's read-only register in hwauto
80 mode as for example omap4 L4_CFG_CLKCTRL
82 - clock-names should contain at least "fck", and optionally also "ick"
83 depending on the SoC and the interconnect target module,
84 some interconnect target modules also need additional
85 optional clocks that can be specified as listed in TRM
86 for the related CLKCTRL register bits 8 to 15 such as
87 "dbclk" or "clk32k" depending on their role
89 - ti,hwmods optional TI interconnect module name to use legacy
92 - ti,no-reset-on-init interconnect target module should not be reset at init
94 - ti,no-idle-on-init interconnect target module should not be idled at init
96 Example: Single instance of MUSB controller on omap4 using interconnect ranges
97 using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
99 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
100 compatible = "ti,sysc-omap2";
101 ti,hwmods = "usb_otg_hs";
105 reg-names = "rev", "sysc", "syss";
106 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
108 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
109 SYSC_OMAP2_SOFTRESET |
110 SYSC_OMAP2_AUTOIDLE)>;
111 ti,sysc-midle = <SYSC_IDLE_FORCE>,
114 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
117 <SYSC_IDLE_SMART_WKUP>;
119 #address-cells = <1>;
121 ranges = <0 0x2b000 0x1000>;
124 compatible = "ti,omap4-musb";
126 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
128 usb-phy = <&usb2_phy>;
133 Note that other SoCs, such as am335x can have multipe child devices. On am335x
134 there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
135 instance as children of a single interconnet target module.