1 ML-AHB interconnect bindings
3 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
4 a Cortex-M subsystem with dedicated memories.
5 The MCU SRAM and RETRAM memory parts can be accessed through different addresses
6 (see "RAM aliases" in [1]) using different buses (see [2]) : balancing the
7 Cortex-M firmware accesses among those ports allows to tune the system
10 [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf
11 [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
14 - compatible: should be "simple-bus"
15 - dma-ranges: describes memory addresses translation between the local CPU and
16 the remote Cortex-M processor. Each memory region, is declared with
18 - param 1: device base address (Cortex-M processor address)
19 - param 2: physical base address (local CPU address)
20 - param 3: size of the memory region.
22 The Cortex-M remote processor accessed via the mlahb interconnect is described
27 compatible = "simple-bus";
30 dma-ranges = <0x00000000 0x38000000 0x10000>,
31 <0x10000000 0x10000000 0x60000>,
32 <0x30000000 0x30000000 0x60000>;
34 m4_rproc: m4@10000000 {