1 Mediatek apmixedsys controller
2 ==============================
4 The Mediatek apmixedsys controller provides the PLLs to the system.
8 - compatible: Should be one of:
9 - "mediatek,mt2701-apmixedsys"
10 - "mediatek,mt2712-apmixedsys", "syscon"
11 - "mediatek,mt6797-apmixedsys"
12 - "mediatek,mt7622-apmixedsys"
13 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
14 - "mediatek,mt7629-apmixedsys"
15 - "mediatek,mt8135-apmixedsys"
16 - "mediatek,mt8173-apmixedsys"
17 - #clock-cells: Must be 1
19 The apmixedsys controller uses the common clk binding from
20 Documentation/devicetree/bindings/clock/clock-bindings.txt
21 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
25 apmixedsys: clock-controller@10209000 {
26 compatible = "mediatek,mt8173-apmixedsys";
27 reg = <0 0x10209000 0 0x1000>;