1 Marvell Armada AP806 System Controller
2 ======================================
4 The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
5 SoCs. It contains system controllers, which provide several registers
6 giving access to numerous features: clocks, pin-muxing and many other
7 SoC configuration items. This DT binding allows to describe these
10 For the top level node:
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP806 system controller
21 The Device Tree node representing the AP806 system controller provides
24 - 0: clock of CPU cluster 0
25 - 1: clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be: "marvell,ap806-clock"
32 - #clock-cells: must be set to 1
37 For common binding part and usage, refer to
38 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
41 - compatible must be "marvell,ap806-pinctrl",
43 Available mpp pins/groups and functions:
44 Note: brackets (x) are not part of the mpp name for marvell,function and given
45 only for more detailed description in this document.
48 ================================================================================
49 mpp0 0 gpio, sdio(clk), spi0(clk)
50 mpp1 1 gpio, sdio(cmd), spi0(miso)
51 mpp2 2 gpio, sdio(d0), spi0(mosi)
52 mpp3 3 gpio, sdio(d1), spi0(cs0n)
53 mpp4 4 gpio, sdio(d2), i2c0(sda)
54 mpp5 5 gpio, sdio(d3), i2c0(sdk)
56 mpp7 7 gpio, sdio(d4), uart1(rxd)
57 mpp8 8 gpio, sdio(d5), uart1(txd)
58 mpp9 9 gpio, sdio(d6), spi0(cs1n)
59 mpp10 10 gpio, sdio(d7)
60 mpp11 11 gpio, uart0(txd)
61 mpp12 12 gpio, sdio(pw_off), sdio(hw_rst)
68 mpp19 19 gpio, uart0(rxd), sdio(pw_off)
72 For common binding part and usage, refer to
73 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
77 - compatible: "marvell,armada-8k-gpio"
79 - offset: offset address inside the syscon block
82 ap_syscon: system-controller@6f4000 {
83 compatible = "syscon", "simple-mfd";
84 reg = <0x6f4000 0x1000>;
87 compatible = "marvell,ap806-clock";
92 compatible = "marvell,ap806-pinctrl";
96 compatible = "marvell,armada-8k-gpio";
101 gpio-ranges = <&ap_pinctrl 0 0 19>;
111 For common binding part and usage, refer to
112 Documentation/devicetree/bindings/thermal/thermal.txt
114 The thermal IP can probe the temperature all around the processor. It
115 may feature several channels, each of them wired to one sensor.
118 - compatible: must be one of:
119 * marvell,armada-ap806-thermal
120 - reg: register range associated with the thermal functions.
123 - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
124 to this IP and represents the channel ID. There is one sensor per
125 channel. O refers to the thermal IP internal channel, while positive
126 IDs refer to each CPU.
129 ap_syscon1: system-controller@6f8000 {
130 compatible = "syscon", "simple-mfd";
131 reg = <0x6f8000 0x1000>;
133 ap_thermal: thermal-sensor@80 {
134 compatible = "marvell,armada-ap806-thermal";
136 #thermal-sensor-cells = <1>;