1 Marvell Berlin SoC Family Device Tree Bindings
2 ---------------------------------------------------------------
4 Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
5 shall have the following properties:
7 * Required root node properties:
8 compatible: must contain "marvell,berlin"
10 In addition, the above compatible shall be extended with the specific
11 SoC and board used. Currently known SoC compatibles are:
12 "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
13 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
14 "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
15 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
16 "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
21 model = "Sony NSZ-GS7";
22 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
27 * Marvell Berlin2 chip control binding
29 Marvell Berlin SoCs have a chip control register set providing several
30 individual registers dealing with pinmux, padmux, clock, reset, and secondary
31 CPU boot address. Unfortunately, the individual registers are spread among the
32 chip control registers, so there should be a single DT node only providing the
33 different functions which are described below.
36 - compatible: shall be one of
37 "marvell,berlin2-chip-ctrl" for BG2
38 "marvell,berlin2cd-chip-ctrl" for BG2CD
39 "marvell,berlin2q-chip-ctrl" for BG2Q
40 - reg: address and length of following register sets for
41 BG2/BG2CD: chip control register set
42 BG2Q: chip control register set and cpu pll registers
44 * Marvell Berlin2 system control binding
46 Marvell Berlin SoCs have a system control register set providing several
47 individual registers dealing with pinmux, padmux, and reset.
50 - compatible: should be one of
51 "marvell,berlin2-system-ctrl" for BG2
52 "marvell,berlin2cd-system-ctrl" for BG2CD
53 "marvell,berlin2q-system-ctrl" for BG2Q
54 - reg: address and length of the system control register set
56 * Clock provider binding
58 As clock related registers are spread among the chip control registers, the
59 chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
60 SoCs share the same IP for PLLs and clocks, with some minor differences in
61 features and register layout.
64 - #clock-cells: shall be set to 1
65 - clocks: clock specifiers referencing the core clock input clocks
66 - clock-names: array of strings describing the input clock specifiers above.
67 Allowed clock-names for the reference clocks are
68 "refclk" for the SoCs osciallator input on all SoCs,
69 and SoC-specific input clocks for
70 BG2/BG2CD: "video_ext0" for the external video clock input
72 Clocks provided by core clocks shall be referenced by a clock specifier
73 indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
74 for the corresponding index mapping.
76 * Pin controller binding
78 Pin control registers are part of both register sets, chip control and system
79 control. The pins controlled are organized in groups, so no actual pin
80 information is needed.
82 A pin-controller node should contain subnodes representing the pin group
83 configurations, one per function. Each subnode has the group name and the muxing
86 Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
87 a 'function' in the pin-controller subsystem.
89 Required subnode-properties:
90 - groups: a list of strings describing the group names.
91 - function: a string describing the function used to mux the groups.
95 chip: chip-control@ea0000 {
96 compatible = "marvell,berlin2-chip-ctrl";
98 reg = <0xea0000 0x400>;
99 clocks = <&refclk>, <&externaldev 0>;
100 clock-names = "refclk", "video_ext0";
102 spi1_pmux: spi1-pmux {
108 sysctrl: system-controller@d000 {
109 compatible = "marvell,berlin2-system-ctrl";
110 reg = <0xd000 0x100>;
112 uart0_pmux: uart0-pmux {
117 uart1_pmux: uart1-pmux {
122 uart2_pmux: uart2-pmux {